Italtel S.p.a.

Other

Riccardo Gemelli

Marco Pavesi

Giuseppe De Blasio

Mauro Ferloni

Fabio De Pieri

Salvatore Matteo Crudo

Maurizio Corradini

Maurizo Grassi

Giacomo Accattoli

Maurizio Grassi

The invention relates to a method of routing or compressing packets destination address through an electronic routing or compressing device, the packets destination address being n bit packets and having address indicative of a desired destination, the address being classless, the routing device having at least a data base of prefix entries, each of which containing entries corresponding to a desired output data link, the method having the steps of: a) generating an address mask until an entry matching a masked address obtained by making an AND operation between the packets destination address and the address mask, is found in the data; the address mask having a number of bit equal to that of the packets destination address and having, starting from the most significant n-bit equal to 1 and the remaining i bit equal to 0, with 0&#x3c;=u&#x3c;=b.1, with the first generated mask having i=0 or i=1, b) if a match is found, stopping the generation of masked address and outputting the output data link corresponding to the match, c) if no match is found, outputting a message indicating that no output data link was found.

Method and device for routing or compressing packets destination address containing classless address

A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding

The invention concerns an automated method to generate the Cyclic Redundancy Check, or CRC, of data packets, minimizing computing time, particularly for the transmission of recursively embedded packets in packet-switching networks, particularly able to carry out the calculation even in case the packet length (as number of bits) is not a multiple integer of processed word width. The invention also concerns the CRC and checksum checking and computing machines carrying out the described calculation.

Automated method for generating the cyclic redundancy check for transmission of multi-protocol packets

A clock signal generation and distribution system for a prototyping apparatus of an electronic system comprises at least one clock signal generation and distribution subsystem for distributing at least one clock signal to the prototyped electronic system implemented by the prototyping apparatus through a clock signal distribution network of the prototyping apparatus. The at least one clock signal generation and distribution subsystem comprises a clock source selector for selecting the at least one clock signal to be distributed to the prototyped electronic system among a group of source clock signals, the group including at least one first source clock signal derived from the prototyped electronic system and at least one second source clock signal not derived from the prototyped electronic system.

Clock generation system for a prototyping apparatus

A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, or FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through as multiple point-to-point buses to transfer signals two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol

A daughter board () is provided for a prototyping system (). The daughter board includes a first surface for facing a mother board () of the prototyping system, and a second surface opposed thereto. The daughter board further includes a connector () for a corresponding socket () of the mother board arranged on the first surface. The connector includes multiple elements (), each one including an insulating support and multiple leads. The daughter board also includes multiple contacts () for corresponding functional terminals of a programmable device () arranged on the second surface. Each contact is connected to a corresponding lead () of the connector. The elements of the connector are arranged along the edges of a regular polygon.

Growing community of inventors

S. Colombano/L, Italy

Riccardo Gemelli