Sharp Kabushiki Kaisha Corporation

Ricardo T Shichiku

Shinichi Yoshida

Tsuyoshi Muramatsu

Manabu Onozaki

Yasuhiro Matsuura

From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.

Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium

An image operation processing apparatus is connected to a memory. The apparatus processes, by accessing the memory, a data packet including instruction information and an address of a prescribed address space. The apparatus realizes an address translation process for translating the address included in an incoming data packet to an address of a partial address space smaller than the prescribed address space. It further realizes a memory access process for accessing the memory in accordance with the address translated by the address translation process. Finally, it performs a process in accordance with the instruction information included in the data packet.

Image operation processing apparatus storing discrete data efficiently in a memory and operating method thereof

A digital filter processing device receives image data of a frame in the order of time series in scanning the frame for carrying out a filter process for every group of image data corresponding to each of a plurality of regions of a predetermined size in the frame. The device receives image data in the order of time series of the scanning operation of a frame to multiply the input image data by a corresponding filter coefficient. This multiplied result is accumulated for every group to be output as an accumulation result. As a result, a region for storing a multiplied result which is an intermediate result of the filter process and an operation for reading out the multiplied result from the storage region for accumulation can be eliminated. Therefore, a filtering process of a frame can be carried out at high speed and in real-time.

Digital filter processing device

A data driven processor includes an H register storing output destination information in path connection verification, and a circuit for selectively providing a data packet to one of a plurality of output ports according to a path verification flag and destination information included in an input data packet and the contents of the H register. The processor 250 may further include a circuit for applying a data packet to an image memory unit according to a path verification flag included in the input data packet and the contents of the H register, and a circuit for directly providing to the output processing unit a data packet for testing returned from an image memory unit according to the path verification flag thereof. A data driven information processing device including a plurality of data driven processors and a method of verifying a path connection in this data driven information processing device are also disclosed.

Growing community of inventors

Kashihara, Japan

Ricardo T Shichiku