International Business Machines Corporation

Ricardo Sedillos Padilla

Todd Charles Sorenson

Wang Ping He

David V Valverde

Matthew J Kalos

Brian Jeffrey Corcoran

Richard Albert Welp

Larry Juarez

Enrique Q Garcia

Stephen LaRoux Blinick

Mark Elliott Hack

Charles Scott Cardinell

Herve G P Andre

Yolanda Colpo

Nikhil Khandelwal

Stefan Lehmann

James Chien-Chiung Chen

Matthew Charles Compton

Kerri Renee Shotwell

Louis Daniel Echevarria

Lourdes Magally Gee

Benjamin S Terris

Lucien Mirabeau

Thomas Holderness Daily

Man Wah Ma

Steve P Wallace

Jason A Ogroski

Stephen La Roux Blinick

Provided are a computer program product, system, and method for processing main cause errors and sympathetic errors in devices in a system. Error data for the devices in the system are analyzed to determine a main cause error for one of the devices that cause at least one sympathetic error in the system. A main cause event object for the determined main cause error and at least one sympathetic event object for the determined at least one sympathetic error resulting from the main cause error are generated. A determination is made from the at least one sympathetic event object of at least one sympathetic event action to perform. The determined at least one sympathetic event action is performed to recover from the at least one sympathetic error represented by the at least one sympathetic event object providing the at least one sympathetic event action.

Processing main cause errors and sympathetic errors in devices in a system

Provided are a computer program product, system, and method for embedding and executing trace functions in code to gather trace data. A plurality of trace functions are embedded in the code. For each embedded trace function, a trace level is included indicating code to which the trace applies. The trace level comprises one of a plurality of levels. During the execution of the code, the embedded trace functions having one of the levels associated with a specified at least one level specified are executed. The embedded trace functions associated with at least one level not comprising one of the at least one specified level are not invoked.

Embedding and executing trace functions in code to gather trace data

According to one embodiment, a method for handling errors includes detecting that an error has occurred in a machine in a system, determining an error ID associated with the error, determining that the error should be reported to a host system for further analysis based on the error ID, determining that one or more actions should be taken by the system based on the error ID, and sending information corresponding to the error to the host system after it is determined that the error should be reported to the host system. In another embodiment, a system includes a processor and logic for performing the method. According to another embodiment, a computer program product includes a computer readable storage medium having computer readable code embodied therewith for performing the method. Other methods, systems, and computer program products are also described according to more embodiments.

Systems for agile error determination and reporting and methods thereof

A method, system and computer program product for logging and identifying microcode errors in a computing environment is provided. Each of a plurality of errors in the microcode is logged using a plurality of error logging commands. Each of the plurality of errors is indexed to generate a plurality of indexed errors. A plurality of unique keys is associated to each of the plurality of indexed errors. A master index of the plurality of unique keys is created.

Automated microcode detected error index generation

An apparatus, system, and method are provided for updating a code image. The apparatus, system, and method include a loader for loading a new code image into a temporary memory location separate from the memory location occupied by the old code image. A conversion module of the new code image executes and selectively reconciles incompatibilities between the old code image and the new code image. In one aspect, once incompatibilities are reconciled, a copy module copies the new code image into the memory space occupied by the old code image.

Apparatus, system, and method for updating an embedded code image

In one embodiment, a first processor of a multiprocessor system, encounters an exception and jumps to exception handler code at an architecture-defined exception vector. The processor is directed to a data structure which provides a programmable exception vector to additional exception handler code. This additional code may be executed as if it were located at the architecture-defined exception vector. Other embodiments are described and claimed.

Exception handling in a multiprocessor system

An apparatus, system, and method are disclosed for communicating binary data using a self-descriptive binary data structure. The binary data structure also may be referred to as a microcode reconstruct and boot (MRB) image. The binary data structure includes a plurality of data segments, a target data set, and a data structure descriptor. Each of the data segments has a data segment header and data field. The target data set is stored within the data field and may be an executable. The data structure descriptor is descriptive of the binary data structure and identifies the location of the target data set within the data field. The binary data structure is self-descriptive in that the location of an individual target data set may be identified by the data structure descriptor.

Apparatus, system, and method for communicating a binary code image

A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

Multiplex execution-path system

An error handling method is provided for processing adapter errors. Rather than executing a disruptive controller hardware reset, an error handling routine provides instructions for a reset operation to be loaded and executed from cache while the SDRAM is in self-refresh mode and therefore unusable.

Management of memory controller reset

An apparatus, system, and method are disclosed for fastload code update on a communications adapter. The apparatus includes an image load module, a memory initialization module, and an image overlay module. The image load module is configured to load a copy of a new code image in a memory on the communications adapter. The memory also concurrently stores a copy of an old code image used by the communications adapter. The memory initialization module is configured to invoke the new code image to perform a memory initialization operation. The memory initialization module may perform the memory initialization operation concurrently with ongoing I/O requests possibly accepted, but not necessarily processed, by the old code image. The image overlay module is configured to overlay the old code image with the new code image. The fastload code update minimizes the time that the communications adapter is off-line to overlay the old code image with the new code image and reinitialize the communications adapter.

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Tucson, AZ, United States of America

Ricardo Sedillos Padilla