Xilinx, Inc.

Rhona Wade

John Edward Mcgrath

Julian Haines

Gourav Modi

Embodiments herein describe a hardened fractional resampler that includes a fixed filter that supports simultaneous processing of N input samples with minimal additional combinational logic and no additional multipliers. In one embodiment, the fractional resampler is implemented in an integrated circuit using hardened circuit. The embodiments below exploit a pattern in the order filter phases in fractional resampling systems (such as a SSR resampling system) to use filter phases in a single fixed filter to process multiple input samples in parallel, where these filter phases would have been unused in previous resampling systems.

Polyphase filter control scheme for fractional resampler systems

Embodiments herein describe an integrated circuit with a digital front end (DFE) that includes multiple hardened mixers that can be configured to support multiple different radio paths. The DFE provides the ability to distribute the processing across the multiple mixers, which can be combined and synchronized to create a larger mixer or may be used in other combinations to create multiple discrete mixers.

Reconfigurable mixer design enabling multiple radio architectures

An example clock synthesizer, having a single-phase clock signal as input and generating an output clock, includes a phase decrementer configured to receive a fractional period value, configured to, responsive to the fractional period value, maintain a fractional count, and configured to accumulate residual phase from cycle-to-cycle of the output clock. A clock generator provides an integer-count-zero signal indicative of an integer portion of the fractional count reaching zero. A clock phase selector is configured to provide a signal having a fractional portion of the fractional count. A phase generator and combiner is coupled to an output of the clock generator, and an output of the clock phase selector, and is configured to provide the output clock.

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Dublin, Ireland

Rhona Wade