Teledyne E2v Semiconductors Sas

Rémi Laube

Jérôme Ligozat

Marc Stackler

Quentin Béraud-Sudreau

Simon Joret

Matthieu Martin

Quentin Beraud-sudreau

Etienne Bouin

Julien Cochard

St éphane Breysse

Quentin Bureau-Sudreau

The invention relates to a method for determining the phase difference between a first clock signal (CK) received by a first electronic component (CE) and a second clock signal (CK) received by a second electronic component (CE), comprising the steps of:

Method for determining the phase difference between a first clock signal received by a first electronic component and a second clock signal received by a second electronic component

The invention relates to a method for synchronizing a plurality of analogue-digital or digital-analogue converters (CONV_k), the converters (CONV_k) all being connected to a control unit (UC), and to a clock (CLK) that has a predefined clock period (T), the converters being also chained step-by-step so as to form a chain of converters, each converter (CONV_k) generating an internal synchronization signal (internal_sync_k) configured to supply a time reference on the transmission of data by the converter (CONV_k). The method allows the synchronization of the converters to be guaranteed using a process of learning and of configuration of the converters. The method allows any line distance constraint on the synchronization signal to be overcome.

Method for synchronizing analogue-digital or digital-analogue converters, and corresponding system

A method for synchronizing analog data (Data_ana, Data_ana) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C, C), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START, START) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R, R) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.

Method for synchronising analogue data at the output of a plurality of digital/analogue converters

In an architecture for processing data comprising a control unit and converters CNto be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgethat sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftfurthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.

Method for synchronizing data converters by means of a signal transmitted from one to the next

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Veurey-Voroize, France

Rémi Laube