Intel Corporation

Intel Ndtm US LLC

Rezaul Haque

Kerry Dean Tedrow

Ahsanur Rahman

Lady Nataly Pinilla Pico

Bayan Nasri

Dhanashree R Kulkarni

Darshak A Udeshi

Ali Khakifirooz

Aliasgar S Madraswala

Bo Li

Shantanu R Rajwade

Tzu-Ning Fang

Matthew Goldman

Narayanan Ramanan

Saad Monasa

Matin Amani

Netra Mahuli

Nathan Chrisman

Dung C Nguyen

Seong Je Park

Karthi Ramamurthi

Kevin P Flanagan

A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.

Memory cell sensing circuit with adjusted bias from pre-boost operation

Systems, apparatuses and methods may provide for technology that applies a first set of control signals to even bitlines in NAND memory and senses voltage levels of the even bitlines during an even sensing time period. The technology may also apply a second set of control signals to odd bitlines in the NAND memory, and sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period.

Staggered active bitline sensing

The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.

Memory access control

A wireless device that includes a memory device having an engine to execute a voting algorithm to average a memory cell data sensing result over time to provide a charge placement in the memory cell.

Data storage and processing algorithm for placement of multi-level flash cell (MLC) VT

A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.

Multi-level memory cell sensing

In the multi level/bit per cell memory array, a flag cell indicates pseudo single bit per cell configuration for one or more cells of the memory array. The output of the cell or cells associated with the flag cell is a single bit when the flag cell is set. The cell or cells associated with the flag cell operate as multi level/bit per cell cells when the flag cell is not set. The flag cell of the memory array may also be a multi level/bit per cell cell that is read to provide a single bit output. Multiple flag cells may be provided and associated with various cells or groups of cells so that these cells or groups of cells may be operated in a user selectable pseudo single bit configuration.

Memory array with pseudo single bit memory cell and method

During a program verify sensing operation, a tracking signal may be generated to match a sense amplifier signal. A data stream from a sequence generator may be held at a pass/hold logic until the tracking signal reaches a trip point. The data stream may be subsequently latched at a main latch with the sense amplifier signal.

Program-verify sensing for a multi-level cell (MLC) flash memory device

A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.

Multi-level cell serial-parallel sense scheme for non-volatile flash memory

Growing community of inventors

Folsom, CA, United States of America

Rezaul Haque