Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Reza Mushtag Bacchus

Melvin K Benedict

Eric L Pope

Stephen F Contreras

John Norton

Vincent Hung Nguyen

Troy Anthony Della Fiora

Keith A Sauer

Robert C Elliott

James Jeffery Schulze

Chi Kim Sides

Mitchel E Wright

Darrel G Gaston

Chun-Pin Huang

Michael Lawrence Sabotta

Paul A Santeler

Kevin T Lim

Raghavan V Venugopal

Thomas D Rhodes

Timothy Majni

Jim W Brainard

Mujeeb Rehman

Hubert E Brinkmann, Jr

Kenneth T Brown

Chi-li-ma Harnold

An apparatus comprising: a drive carrier assembly (DCA) including; an energy storage device having at least a portion thereof encased by a housing; and a printed circuit assembly to detect a power failure of a host computing device, wherein the printed circuit assembly has a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device.

Device carrier assemblies

In some examples, a memory module includes an error status indicator, an error address register, and error tracking circuitry. The error tracking circuitry may detect that memory data stored at a memory address for the memory module includes an error. In response, and without overwriting the memory data stored at the memory address, the error tracking circuitry may set the error status indicator and store the memory address in the error address register.

Memory module error tracking

An example apparatus comprises a drive carrier assembly which may include a memory device, and an energy storage device having at least a portion thereof encased in a housing. In some examples, the apparatus may include a printed circuit assembly to detect a power failure of a host computing device. The printed circuit assembly, may have a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device.

Drive carrier assemblies

An example memory device comprises at least one memory region; and a controller to determine exceeding of a throttling threshold and to throttle processing of access requests for the at least one memory region.

Quality of service based memory throttling

One example includes a system. The system includes an error injection system. The error injection system includes an error injector to store a programmable control structure to define a memory error. The error injector being further used to inject the memory error into a respective one of a plurality of memory storage elements associated with a memory system at a predetermined address via an address controller and to determine if the memory error at the predetermined address associated with the respective one of the plurality of memory storage elements is corrected via error-correcting code (ECC) memory associated with the memory system.

DRAM-level error injection and tracking

A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.

Differential serial memory interconnect

In one implementation, a memory module with on-die error correction code (ECC) with scrub operation capabilities and a programmable patrol scrub period is coupled to a memory controller that causes error correction operations to perform based on a power status of an energy storage device.

Patrol scrub periods based on power status

A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Volatile memory device with automatic lower power state

An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Memory module voltage regulator module (VRM)

An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

Memory access signal detection utilizing a tracer DIMM

An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Techniques are described for assigning an application thread to a cache. A newly created application thread may be assigned to a plurality of caches. The cache assignment that optimizes performance may be determined. The newly created application thread may be associated with the determined cache.

Application thread to cache assignment

Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.

Method and system for power-efficient and non-signal-degrading voltage regulation in memory subsystems

In at least some embodiments, a system comprises a processor and a memory coupled to the processor. The memory stores processor performance utility instructions and performance adjustment instructions. When executed, the processor performance utility instructions are configured to cause activities of the processor to be counted and to cause a processor utilization value to be determined based on the counts. When executed, the performance adjustment instructions are configured to adjust the processor utilization value based on a comparison of the processor's current operating frequency and maximum operating frequency.

Systems and methods to determine processor utilization

A method includes querying a memory to determine what type of voltage the memory requires and applying the proper operating voltage to the memory based on the query. An apparatus that supports different memory types is also disclosed.

Growing community of inventors

Spring, TX, United States of America

Reza Mushtag Bacchus