Qualcomm Incorporated

Reza Mohammadpourrad

Helena Deirdre O'Shea

Philip Michael Clovis

Jianguo Yao

ZhenQi Chen

Scott Davenport

Zeeshan Shafaq Syed

Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

On-chip clock generator calibration

Changing operating states of a PHY interface which includes a plurality of blocks, changing operating states of a PHY interface includes: receiving parameters indicating desired feature settings of the plurality of blocks for changing the operating state of the PHY interface; and enabling the desired feature settings in a sequence, the sequence based on dependencies between the feature settings, the dependencies being stored in a dependency table.

Frequency and power management

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San Diego, CA, United States of America

Reza Mohammadpourrad