Motorola Corporation

Reza Moazzami

Papu D Maniar

Jon T Fitch

Keith E Witek

Sergio A Ajuria

C Joseph Mogab

Andrew C Campbell

Jerry Gelatos

Robert E Jones

Robert Edwin Jones, Jr

A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.

Capacitor having a metal-oxide dielectric

Process for forming a capacitor having a metal-oxide dielectric

The present invention includes a semiconductor device having a layer including an elemental metal and its conductive metal oxide, wherein the layer is capable being oxidized or reduced preferentially to an adjacent region of the device. The present invention also includes processes for forming the devices. Substrate regions, silicon-containing layers, dielectric layers, electrodes, barrier layers, contact and via plugs, interconnects, and ferroelectric capacitors may be protected by and/or formed with the layer. Examples of elemental metals and their conductive metal oxides that may be used with the present invention are: ruthenium and ruthenium dioxide, rhenium and rhenium dioxide, iridium and iridium dioxide, osmium and osmium tetraoxide, or the like.

Semiconductor device having a reducing/oxidizing conductive material

A method for forming an air region or an air bridge overlying a base layer (12). Air regions (20a, 20b, 28a, and 48) are formed overlying the base layer (12) to provide for improved dielectric isolation of adjacent conductive layers, provide air-isolated conductive interconnects, and/or form many other microstructures or microdevices. The air regions (20a, 20b, 28a, and 48) are formed by either selectively removing a sacrificial spacer (16a and 16b) or by selectively removing a sacrificial layer (28, 40). The air regions (20a, 20b, 28a, and 48) are sealed, enclosed, or isolated by either a selective growth process or by a non-conformal deposition technique. The air regions (20a, 20b, 28a, and 48) may be formed under any pressure, gas concentration, or processing condition (i.e. temperature, etc.). The air regions (20a, 20b, 28a, and 48) may be formed at any level within an integrated circuit.

Semiconductor structure having an air region and method of forming the

Process for forming a semiconductor device having a reducing/oxidizing

Method of forming a semiconductor structure having an air region

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Austin, TX, United States of America

Reza Moazzami