Hewlett-packard Development Company, L.p.

Reynaldo V Villavelez

Paul I Mikulan

Ning Ge

Xin Ping Cao

Chien-Hua Chen

Michael W Cumbie

Joseph M Torgerson

Lawrence H White

Donald W Schulte

Boon Bing Ng

Erik D Ness

Terry E McMahon

David B Novak

Chris Bakker

Chaw Sing Ho

Kenneth J Stewart

Mun Hooi Yaow

Teck-Khim Neo

Lonnie Byers

Bjorn Warloe

Chaw-Sing Ho

Michael Allen Godwin

Lui Cheat Thin

A thermal contact device may include a thermal contact die embedded in a moldable material. The thermal contact die may include a number of resistors integrated into the thermal contact die, and a number of heater drivers integrated into the thermal contact die and electronically coupled to the resistors. The moldable material is coplanar with a thermal contact side of the thermal contact device. Further, the moldable material includes at least one gradient edge along a medium feed path.

Thermal contact dies

The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.

Integrated circuits

In some examples, a heater assembly for a pattern forming system includes a support, and heating elements mounted on the support, where the heating elements are to, in response to activation of the heating element, produce heat directed towards a target to form a pattern on the target. A heat sink is thermally connected to the heating elements and comprising a pattern of heat dissipation surfaces comprising channels to dissipate heat produced by the heating elements.

Dissipating heat of heating elements

The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.

Dischargeable electrical programmable read only memory (EPROM) cell

A memory cell for a printhead includes a substrate with a source and a drain. The substrate further includes a channel located between the source and the drain and surrounding the drain. The drain can include a first rounded closed curved structure. The memory cell can include a floating gate and a control gate. The floating gate can include a second rounded closed curve structure located above the channel and below the control gate. The control gate is capacitively coupled to the floating gate.

Memory cell having closed curve structure

In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.

Fluid ejection devices comprising memory cells

Addressing an EPROM on a printhead is described. In an example, a printhead includes an electronically programmable read-only memory (EPROM) having a bank of cells arranged in rows and columns, each of the cells having a addressing port, a row select port, and a column select port. A conductor is coupled to the addressing portion of each of the cells. A shift register circuit is coupled to at least one of the row select port and the column select port of each of the cells, the shift register circuit storing samples of an input signal responsive to a plurality of clock signals. A decoder is coupled to the shift register circuit to provide the input signal based on a logical combination of a plurality of data signals and at least a portion of the clock signals.

Addressing an EPROM on a printhead

A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer.

Memory cell that prevents charge loss

A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.

A thermal inkjet printhead may include a substrate and a resistive layer. A thermal resistor may be formed in the resistive layer. A first metal layer may be between the substrate and a resistive layer having a thickness to form a power bus. A dielectric layer may be between the first metal layer and the resistive layer.

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Corvallis, OR, United States of America

Reynaldo V Villavelez