Bitmicro Networks, Inc.

Bitmicro LLC

Other

Rey H Bruce

Ricardo H Bruce

Noeme Paz Mateo

Elsbeth Lauren Tagayo-Villapaña

Joel Alonzo Baylon

Joey B Climaco

Raquel Bautista David

Patrick Digamon Bugayong

Ricky Sevilla Nite

Marizonne Operio Fuentes

Marlon Basa Verdan

Bernard Sherwin Leung Chiw

Shielou Vicencio Estrada

Federico Zalzos Sambilay, Jr

Shun Hang Luk

Dave L Bultman

In an embodiment of the invention, an apparatus comprises: a data storage device comprising a first prefetch buffer, a second prefetch buffer, and a third prefetch buffer; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer; and wherein any of the prefetch buffers is configured to store prefetch data. The prefetch data is available to a host that sends a memory read transaction request to the data storage device. In another embodiment of the invention, a method comprises: storing prefetch data in any one of a first prefetch buffer, a second prefetch buffer, or a third prefetch buffer in a storage device; wherein the second prefetch buffer and the third prefetch buffer are both coupled in parallel to the first prefetch buffer. The prefetch data is available to a host that sends a memory read transaction request to a data storage device.

Data storage system with configurable prefetch buffers

A solution for performing reduced latency memory read transactions is disclosed. In one example, a storage apparatus has a memory array that includes: a flash device having a data register, a memory interface coupled to the memory array and a buffer set that includes at least one buffer suitable for use as a prefetch buffer. The memory interface, in response to a memory read transaction request, performs a read operation and, if stored data exists within the memory array that meets a prefetch selection criterion, also performs an internal read operation. The internal read operation includes allocating a prefetch buffer in the buffer set and storing the data as prefetch data in the prefetch buffer. If the memory interface receives a second memory read transaction request for data that is currently available as prefetch data, the memory interface responds by performing a forwarding transaction that includes retrieving the prefetch data from the prefetch buffer and forwarding the prefetch data to a host.

Memory transaction with reduced latency

Embodiments of the present invention relate to an apparatus, method, and/or sequence for a distributed ECC that may be used in a storage system. In another embodiment of the invention, an apparatus for handling distributed error correction code (ECC) operations, includes: a plurality of ECC engines configured to perform ECC operations in parallel on multiple data parts; the plurality of ECC engines distributed in parallel to receive some of the multiple data parts that are read from storage media devices and to receive some of the other multiple data parts that are to be written to the storage media devices; and the plurality of ECC engines configured to use respective ECC bytes corresponding to respective ones of the multiple data parts.

Storage system with distributed ECC capability

Distributed ECC engine for storage media

Reduced latency memory read transactions in storage devices

A protocol for providing secured IO device and storage controller handshake protocol; IO device controlled cipher settings, and secured data storage and access in memory. An IO device requesting data transfer with encryption and/or decryption, requests session keys from the processor. The processor generates a fresh public-private key pair for the session. The public key is sent to the requesting IO device; the private key is momentarily saved by the processor for the session. The requesting IO device generates a secret key and its desired cipher setting; furthermore, encrypts the secret key and cipher setting using the public key, and sends secret key and cipher setting to the processor. The processor uses the private key to decrypt the secret key and cipher setting. The cipher setting is used for configuring the data processing core. The secret key is used for encryption and/or decryption of the data being transferred. All keys are not permanently saved.

Input-output device and storage controller handshake protocol using key exchange for data security

Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Multiple chip module and package stacking method for storage devices

A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

Hybrid multi-tiered caching storage system

Multiple chip module and package stacking for storage devices

Due to the integration of multiple I/O device controllers in a storage controller and the need to provide secure and fast data transfers between the I/O devices and the storage controller, an architecture that can perform multiple encrypt/decrypt operations simultaneously is therefore needed to service multiple transfer requests without a negative impact on the speed of transfer and processing. The present invention relates to enhancing Direct Memory Access (DMA) operations between multiple IO devices and a storage controller by adding a Data Processing Core. Exemplary implementations are provided to illustrate the background mechanism used by a DMA controller that minimizes central-processing-unit (CPU) intervention and the multi-channel architecture which allows multiple IO requests to be serviced simultaneously.

Direct memory access controller with encryption and decryption for non-blocking high bandwidth I/O transactions

In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps&#x2014;data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.

Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transfer

A network storage device. In one embodiment, the network storage device of the present invention uses solid-state non-volatile memory (e.g., flash-memory) as a storage medium, and has at least one interface configured for coupling to a computer network. The network storage device of the present invention is accessible to client(s) and/or server(s) of the computer network, and uses solid-state non-volatile memory to store data received therefrom. The network storage device may also be configured to include a memory for caching data to be written to the solid-state non-volatile memory. In order to provide additional storage, the network storage device may also include a peripheral interface or another network interface for coupling to a mass storage device (e.g., a RAID system), and/or another network interface for coupling to a network of mass storage devices. The network storage device may be a stand-alone unit, or may be implemented as part of a network server, or as part of a mass storage device.

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San Jose, CA, United States of America

Rey H Bruce