Qualcomm Incorporated

Qlogic Corporation

Lsi Corporation

Rexford Alan Hill

Aaron Douglass Lamb

Christopher G Lott

Amin Ansari

William Clinton Terrell

Jean Kodama

Harun Muliadi

Tracy Edmonds

Stephen How

Norman Chan

Michael Nishimura

Wayland Joeng

Eric Russell Peterson

Colin Beaton Verrilli

Erich Plondke

Eric W Mahurin

Michael Goldfarb

Andrew Evan Gruber

Natarajan Vaidhyanathan

David J Hoyle

Martin Jess

Jin Won Lee

Jeffrey Gemar

Charles E Nichols

Vito Remo Bica

Jason Edward Podaima

John Logan

Kyle Ernewein

Timothy R Snider

Adrienne Milner

Shambhoo Khandelwal

Haoping Xu

Albert Danysh

Hitesh Kumar Gupta

Piero Zappi

Francisco Perez

John Daniels

Sruthikesh Surineni

Alex Miler

Vito Bica

A method performed by a computing device includes determining a partition for depth-first processing by a multi-layer artificial neural network (ANN) of the computing device. The computing device comprising a processor, on-chip memory, and off-chip memory. The first partition determined based on an amount of on-chip memory used by the first partition, an available amount of on-chip memory, and a size of a write back to the off-chip memory. The method also includes processing, at the device via the multi-layer ANN, an input, using the depth-first processing in accordance with the partition.

Depth-first deep convolutional neural network inference

An aspect of the disclosure relates to a data processing system, including: an input medium configured to include a first set of blocks of data including a first set of block of compressed data and a first set of metadata, respectively; an output medium configured to include a first set of blocks of decompressed data each having a predetermined number of decompressed elements; and a set of single instruction multiple data (SIMD) processors configured to: access the first set of blocks of data from the input medium, respectively; decompress the first set of blocks of compressed data to generate the first set of blocks of decompressed data based on the first set of metadata, respectively; and provide the first set of blocks of decompressed data to the output medium, respectively.

Single instruction multiple data (SIMD) sparse decompression with variable density

The present disclosure describes methods, computer-readable media, and apparatuses for operating neural networks. For example, a first apparatus may receive a set of sparse weight vectors. The first apparatus may compress the set of sparse weight vectors to produce a compressed set of sparse weight vectors. The first apparatus may operate a neural network based on the compressed set of sparse weight vectors. In another example, a second apparatus may receive a set of sparse weight vectors. The second apparatus may perform a sparse computation based on the set of sparse weight vectors, and the performance of the sparse computation may produce one or more partial sums. The second apparatus may operate a neural network based at least in part on the one or more partial sums.

Compression of sparse deep convolutional network weights

A method of exploiting activation sparsity in deep neural networks is described. The method includes retrieving an activation tensor and a weight tensor where the activation tensor is a sparse activation tensor. The method also includes generating a compressed activation tensor comprising non-zero activations of the activation tensor, where the compressed activation tensor has fewer columns than the activation tensor. The method further includes processing the compressed activation tensor and the weight tensor to generate an output tensor.

Exploiting activation sparsity in deep neural networks

A method of constraining data represented in a deep neural network is described. The method includes determining an initial shifting specified to convert a fixed-point input value to a floating-point output value. The method also includes determining an additional shifting specified to constrain a dynamic range during converting of the fixed-point input value to the floating-point output value. The method further includes performing both the initial shifting and the additional shifting together to form a dynamic, range constrained, normalized floating-point output value.

Constraining function approximation hardware integrated with fixed-point to floating-point conversion

In one embodiment, a depth-first deep convolutional network (DCN) having a first convolutional layer having a first first-layer kernel and adapted to convolve a first input and a second convolutional layer having a first second-layer kernel and adapted to convolve a second-layer input. A method for the DCN includes initiating convolution in the first convolution layer of the first input tensor with the first first-layer kernel to generate a value strip for the second input tensor and, prior to completion of the convolution in the first convolution layer, initiating convolution in the second convolution layer of the second input with the first second-layer kernel to generate a value strip for a third layer.

Depth-first convolution in deep neural networks

Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.

Systems and methods for controlling instantaneous current changes in parallel processors

A method, apparatus, and system for an architecture for machine learning acceleration is presented. An apparatus includes a plurality of processing elements, each including a tightly-coupled memory, and a memory system coupled to the processing elements. A global synchronization manager is coupled to the plurality of the processing elements and to the memory system. The processing elements do not implement a coherency protocol with respect to the memory system. The processing elements implement direct memory access with respect to the memory system, and the global synchronization manager is configured to synchronize operations of the plurality of processing elements through the TCMs.

Method, apparatus, and system for an architecture for machine learning acceleration

A computing device may allocate a plurality of blocks in the memory, wherein each of the plurality of blocks is of a uniform fixed size in the memory. The computing device may further store a plurality of bandwidth-compressed graphics data into the respective plurality of blocks in the memory, wherein one or more of the plurality of bandwidth-compressed graphics data each has a size that is smaller than the fixed size. The computing device may further store data associated with the plurality of bandwidth-compressed graphics data into unused space of one or more of the plurality of blocks that contains the respective one or more of the plurality of bandwidth-compressed graphics data.

Storing bandwidth-compressed graphics data

Dynamic clock voltage scaling (DCVS) based on application performance in a system-on-a-chip (SOC), and related methods and processor-based systems are disclosed. In this regard, in one embodiment, a method of providing an application-specific DCVS in a SOC is provided. The method comprises receiving performance data corresponding to at least one performance characteristic of a SOC indicative of an execution performance of an application executing on the SOC. The method also comprises storing the performance data for the application executing on the SOC. The method further comprises, responsive to executing the application on the SOC, determining an application-specific DCVS setting for the application based on the performance data, and setting a DCVS parameter of the SOC based on the determined application-specific DCVS setting for the application. In this manner, an optimal DCVS setting is provided for the SOC to optimize computing resources, thus improving perceived performance of the application.

Dynamic clock voltage scaling (DCVS) based on application performance in a system-on-a-chip (SOC), and related methods and processor-based systems

Methods and structure for reprogramming firmware in a storage controller using a virtual machine management (VMM) environment. A storage process (current firmware) in the storage controller operates in a current virtual machine (VM) under control of a hypervisor. Reprogrammed (new) firmware is loaded into a new virtual machine under control of the hypervisor. The new firmware initializes and directs the current firmware to quiesce its processing. The new firmware also requests the hypervisor to map data in the memory space of the current virtual machine into the memory space of the new virtual machine and to transfer ownership/control of devices and network addresses from the current virtual machine to the new virtual machine. The new firmware operating on the new virtual machine then takes control of the storage controller and resumes processing of requests.

Methods and structure for near-live reprogramming of firmware in storage systems using a hypervisor

A router for use in a network includes a scalable architecture and performs methods for implementing quality of service on a logical unit behind a network port; and for implementing storage virtualization. The architecture includes a managing processor, a supervising processor; and a plurality of routing processors coupled to a fabric. The managing processor has an in-band link to a routing processor. A routing processor receives a frame from the network, determines by parsing the frame, the protocol and logical unit number, and routes the frame to a queue according to a traffic class associated with the logical unit number in routing information prepared for the processors. An arbitration scheme empties the queue in accordance with a deficit round robin technique. If a routing processor detects the frame's destination is a virtual entity, and so is part of a virtual transaction, the router conducts a nonvirtual transaction in concert with the virtual transaction. The nonvirtual transaction accomplishes the intent of the virtual transaction but operates on an actual network port, for example, a storage device.

Router with routing processors and methods for virtualization

Router and methods for distributed virtualization

Router and methods using network addresses for virtualization

Growing community of inventors

San Diego, CA, United States of America

Rexford Alan Hill