Silicon Laboratories Inc.

Rex Wong Tak Ying

Ricky Setiawan

Obaida Mohammed Khaled Abu Hilal

Hua Beng Chan

Axel Thomsen

Alan Lee Westwick

Jeffrey Lee Sonntag

Yushan Jiang

A peak detector including an input transistor, an isolation transistor, at least one load transistor, a buffer, a control transistor, a current source and at least one resistor. The isolation transistor isolates the input and load transistors from the supply voltage for power supply rejection. The buffer, control transistor, current source and resistor(s) bias the input transistor to remain in a saturation region and each load transistor to remain in a triode region. The buffer may be a unity gain buffer. The control transistor may match each load transistor with matching threshold voltages. An input bias circuit may be included to bias an input node to a direct-current voltage. The load transistor(s) may be biased to have so that the output voltage is proportional to a peak voltage of the input node. The peak detector may be configured to detect multiple inputs and may have shared circuitry.

Accurate peak detector

In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Digital oversampling clock and data recovery circuit

In one aspect, a method includes: determining a power mode of a device; setting a first reference voltage level and a second reference voltage level based at least in part on the power mode; and using at least one of the first reference voltage level and the second reference voltage level for comparison against incoming data.

Controlling a reference voltage for a clock and data recovery circuit

A system, USB Type-C connector and method are provided herein to transmit encoded data across a USB cable from a transmitter circuit included within a transmitting port of a USB Type-C connector. The method described herein may generally include detecting a voltage generated at a configuration channel (CC) pin of a transmitting port of a USB Type-C connector, setting a voltage at an output node of the transmitter circuit equal to the voltage detected at the CC pin before the output node of the transmitter circuit is connected to the CC pin, subsequently connecting the output node of the transmitter circuit to the CC pin, and transmitting the encoded data from the transmitter circuit through the CC pin to the USB cable.

System, USB Type-C connector and method to transmit encoded data

Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

Apparatus for gain selection with compensation for parasitic elements and associated methods

Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.

Growing community of inventors

Singapore, Singapore

Rex Wong Tak Ying