Texas Instruments Corporation

Rex Warren Pirkle

Sean Michael Malolepszy

David Joseph Bon

Ronald Andrew Michallick

George Reeves

Gregory George Romas, Jr

Michael Nolan Jervis

Curtis L Harbert

Michael W Perry

In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data.

Defect detection in integrated circuit devices

The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention, dual capillary bond head apparatus includes a rotatable ultrasonic horn with a pair of capillaries for selectably dispensing separate strands of bond wire and for forming bonds on bond targets. According to another aspect of the invention, a method is provided for dual capillary IC wirebonding including steps for using two dual capillary bond heads for contemporaneously attaching non-identical bond wires to selected bond targets on one or more IC package assemblies.

Dual capillary IC wirebonding

The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration.

Process for precision placement of integrated circuit overcoat material

In a method and system for regulating an output voltage, a linear voltage regulator (LVR) includes an adjustable shunt regulator (ASR) having a limited gain, a feedback circuit (FC), and a compensation resistor (CR). The limited gain causes the output voltage of the ASR to change in response to a change in an input current of the ASR. The FC generates a feedback voltage reference in proportion to the output voltage, the feedback voltage reference being provided to the ASR to control the output voltage. The CR is coupled to the ASR and the FC. The input current flows through the CR to provide a compensating voltage across the CR. The compensating voltage is provided to the feedback circuit to compensate the limited gain, thereby providing the output voltage that is substantially independent of the input current.

Output impedance compensation for linear voltage regulators

Embodiments of the present disclosure provide a routing engine, a method of routing a test probe and a testing system employing the router or the method. In one embodiment, the routing engine is for use with a test unit having at least one test probe and includes an analysis unit configured to analyze alternative test probe routing sequences that employ representative circuit chips of a semiconductor wafer to be tested by the test unit. The routing engine also includes a selection unit configured to select at least one of the test probe routing sequences as a test probe path for testing the semiconductor wafer based on a total cost of travel for the test probe path.

Routing engine, method of routing a test probe and testing system employing the same

A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the die passes the sample parameters the die is good and repeat the steps of determining if the die is within specification and measuring the sample parameters until a die fails the measurement test or requires a trimming and if a die fails a measurement test or requires trimming perform 100 percent test and trim.

Selective trim and wafer testing of integrated circuits

A low current blow trim fuse structure and method of forming the trim fuse structure. Oxide steps are placed beneath a trim fuse during prior processing steps. The oxide steps will cause the metal (or polycrystal silicon (poly)) to thin at the point where the metal (or poly) transitions the step, and thus will reduce its cross-sectional area and current carrying capability, making it easier to program the fuse. The oxide steps will serve a further purpose in that, to some extent, it will thermally isolate the trim fuse, thereby causing local heating, making the fuse easier to blow.

Growing community of inventors

Denison, TX, United States of America

Rex Warren Pirkle