Silicon Laboratories Inc.

Cirrus Logic Inc.

Rex T Baird

Michael Henderson Perrott

Yunteng Huang

David M Pietruszynski

Jerrell P Hein

Wesley Ladd Mokry

Matthew M Kostelnik

Itani R Nadi

Mokry Wesley

A technique for expanding an input signal includes receiving the input signal at a first node of a voltage expander and generating a plurality of expanded signals on different outputs of the voltage expander responsive to the input signal. In certain embodiments, each of the expanded signals has a different magnitude at a respective fixed offset from the input signal.

Technique for expanding an input signal

In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In some embodiments, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is 'integrated' by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent 'size' of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block.

Digitally-synthesized loop filter method and circuit particularly useful for a phase locked loop

A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted. An impedance tuning feedback system provides a resistance between two nodes which is proportional to a reference resistance, and preferably incorporates slow digital switching to result in near perturbation-free state changes over the tuning range of the resistance.

Feedback system incorporating slow digital switching for glitch-free state changes

An optical disk pickup system includes an array of photodiodesfor converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitrydrives at least one of the electrical signals as a current across a conductor of a flexible cableA low impedance loadconverts the electrical signal driven across the conductor as a current into a voltage for further processing.

Optical disk pickup using current mode signal exchanges and systems and methods using the same

In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is &ldquo;integrated&rdquo; by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent &ldquo;size&rdquo; of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which requires a small incremental integrated circuit area. The power dissipation of the digital integration block is reduced by incorporating a decimation stage to reduce the required operating frequency of the remainder of the digital integration block.

Digitally-synthesized loop filter circuit particularly useful for a phase locked loop

Impedance tuning circuit

An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used as a rough frequency reference to determine, for an externally-provided frequency reference signal, which of a finite number of discrete frequencies is currently received. The VCO has a frequency range which varies less, as a percentage, than the ratio between possible reference frequency values. Consequently, the VCO is used as a frequency reference to measure the frequency reference signal. An internal signal is generated to indicate to remaining circuitry which of the possible reference frequencies is actually being provided, without requiring use of any dedicated input pins to receive a select signal. An integrated circuit device may be configured for different modes of operation as a function of which reference frequency is provided to the device. Moreover, if one of the available reference clock frequencies is chosen to correspond to an internal test mode, the device may be placed in a test mode without requiring any additional dedicated input pins for that purpose, either.

Integrated circuit incorporating circuitry for determining which of at least two possible frequencies is present on an externally provided reference signal and method therefor

An optical disk pickup system includes an array of photodiodes for converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitry drives at least one of the electrical signals as a current across a conductor of a flexible cable . A low impedance load converts the electrical signal driven across the conductor as a current into a voltage for further processing.

Servo control circuitry includes a digital to analog converter for converting digital servo control data into a pulse width modulated signal. A first conductor transmits the pulse width modulated signal to an external device . A second conductor transmits a reference signal derived from the clock signal to external device , external device differentially receiving the pulse width modulated signal with respect to the reference signal.

Optical servo control circuits and methods using pulse width modulation and offset control for driving an electromechanical motor

A system and method is disclosed for calibrating comparators of an ADC while the ADC continues to operate in an uninterrupted fashion. Groups (banks) of interleaved comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra &ldquo;proxy&rdquo; or replacement comparators. More particularly, at periodic intervals the comparators of one bank may be disconnected from the standard ADC circuitry for calibration or auto-zeroing while the comparators in the remaining bank(s) are left in the data conversion path. In order to prevent a significant degradation in the conversion quality, logic downstream of the comparators provides the necessary adjustments to accommodate for the removal of the comparators and outputs a word of the desired bit length. The multi-bank ADC is particularly advantageous for use with optical data storage systems.

Multi-bank flash ADC array with uninterrupted operation during offset calibration and auto-zero

An optical disk pickup system using current mode signal transmission is disclosed. An operational amplifier has an input for receiving an electrical signal and a feedback loop including a current path of a first transistor of a first size, transistor having a control terminal at a preselected voltage. A conductor is coupled to an output of operational amplifier for transmitting the electrical signal as a current. A second transistor of a second size has a current path in series with a conductor and a control terminal coupled to the preselected voltage, transistors forming a current divider.

Optical disk pickup system using current division signal transmission and methods and optical disk systems using the same

Analog modulator circuitry,includes an integrator,. First switched capacitor circuitry,selectively samples a first amount of charge from a feedback signal and couples that first amount of charge to the first and second inputs of the integrator. Second switched capacitor circuitry,selectively samples a second amount of charge from the feedback signal and couples that second amount of charge to the first and second inputs of the integrator stage to selectively compensate for an offset of an input signal to the integrator with respect to a reference voltage.

Growing community of inventors

Nashua, NH, United States of America

Rex T Baird