Intel Corporation

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Rex Petersen

Robert C Rose

James Ignowski

Jeffrey Paul Witte

John D Wanek

Sean M Welch

Mondira D Pant

Jeremy Glen Slade

Jon Eric Josephson

Aaron M Barton

Pablo Lopez

Methods and systems to detect droop events on-chip, which may include a sensor circuit located adjacent to a voltage node to convert a corresponding voltage to a digital count or value indicative of the voltage. The sensor circuit may include an n-stage ring oscillator and an asynchronous counter. The sensor circuit may include circuitry to capture and convert a phase associated with a count to a binary fractional value to increase voltage resolution. Multiple counts associated with the node may be evaluated at the node to identify minimum and maximum counts and corresponding time stamps. More complex evaluation and control circuitry may be shared amongst a plurality of sensor circuits and may include circuitry to generate and compare counts to one or more variable thresholds, circuitry to average counts over time, and memory to store state values associated with the sensors.

Methods and systems to detect voltage changes within integrated circuits

A method of designing a VLSI chip and a chip designed according to the method are described. The method includes the steps of early consideration of resistive and capacitive values during a VLSI chip design process. The method provides for estimation of signal routes between nodes of functional blocks to be incorporated in the chips. The estimation may be based on a floor plan describing the positioning of the functional blocks, a connectivity description identifying connections between ports of the blocks and physical and mechanical configuration parameters. The functional blocks and design of the layout may be hierarchical in nature. The signal route estimation may be based on control factors such as the specification of signal route establishment algorithms. The next step is to foliate the nodes followed by determining resistance and capacitance values corresponding to all or parts of the estimated signal routes. The resistive and capacitive values may be incorporated into a model and a connectivity net list may be generated.

Resistance and capacitance estimation

A method and system for inserting in-place interconnect repeaters along the paths of interconnects of an integrated circuit is presented. The integrated circuit includes an interconnect layer on which an interconnect is routed, a silicon layer in which repeaters are implemented, and zero or more intervening layers. In accordance with the invention, reserved metal areas are defined on each intervening layer that resides between the interconnect layer and the repeater layer. Each interconnect net that requires a repeater for performance reasons is assigned to a repeater location. A repeater buffer is inserted at the assigned repeater locations. The interconnect net is cut into first and second subnets, which are then respectively connected through the reserved metal areas of the intervening layers to the respective input and output port of the repeater buffer.

In-place method for inserting repeater buffers in an integrated circuit

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Fort Collins, CO, United States of America

Rex Petersen