Harris Corporation

Intersil Americas Inc.

Globespan Virata Corporation

Conexant Systems, Inc.

Intersil Corporation

Silicon Space Technology Corporation

Conexant, Inc.

Rex Everett Lowther

William R Young

Yiqun Lin

Gregg D Croft

Wesley H Morris

David R Gifford

Dale R Setlak

Anthony L Rivoli

James P Furino, Jr

Patrick Anthony Begley

Nicolaas W Van Vonno

Joseph A Czagas

Joseph C Bernier

Dave Gebauer

Robert Lomenic

James D Beason

Gyorgy Bajor

Dennis C Young

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.

Memory circuit incorporating radiation-hardened memory scrub engine

A method of determining electrical parameters of inductive elements includes a novel technique of inverting an impedance matrix representative of said inductive circuit element. The method reduces model simulation time by a factor of 3000. In one embodiment, simulation time of a device model was reduced from 1 hour to less than 3 seconds. The method is suitable for use with circuit element modeling tools, circuit simulation environments, and antenna modeling systems. The method may be applied to inductors, transformers, antennas, etc.

Numerically modeling inductive circuit elements

A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.

Line modeling tool

The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.

Symmetric inducting device for an integrated circuit having a ground shield

Inducting devices having a patterned ground shield with ribbing in an integrated circuit. In one embodiment, an inducting device comprises conductive turns to conduct current, a shield layer and a plurality of ribs. The shield layer is formed a select distance from the conductive turns. The shield layer is patterned into sections of shield to prevent eddy currents. The plurality of ribs are formed from a conductive layer that is positioned between the conductive turns and shield layer. Each rib is electrically coupled to a single associated section of shield. Moreover, each rib is more conductive than its associated section of shield to provide a less resistive current path than its associated section of shield.

Inductor device with patterned ground shield and ribbing

An integrated circuit having an inducting device with a symmetric inductor. The inducting device comprises a first and second inductor. The first inductor is formed in a first conductive layer and is approximately symmetric about a plane of symmetry. The second inductor is formed in a second conductive layer that is at a select vertical distance from the first conductive layer. The second inductor is further approximately laterally aligned with the first inductor.

Solid state inducting device

In one embodiment a substrate,is patterned to have high and low conductive areas,respectively. Metal lines,in dielectric layer,pass transversely over the areas,The areas,interrupt parasitic inductive current induced in the substrate

Parasitic current barriers

An electrostatic discharge locating system may include a plurality of receivers and a central unit. Each receiver may include an antenna. The receivers may receive radio wave signals emanating from an electrostatic discharge event and transmit the signals to the central unit for processing. The central unit may determine the location of an electrostatic discharge event from the relative time of signal reception or the signal amplitudes along with predetermined locations of the receivers.

Electrostatic discharge locating apparatus and method

Growing community of inventors

Palm Bay, FL, United States of America

Rex Everett Lowther