International Business Machines Corporation

Rex E McCrary

Timothy V Lee

Gary B Hoch

Stephanie P Payne

Daniel Petkevich

Hai V Pham

Frederick Charles Yentz

Robert Chih-Tsin Eng

Eric H Stelzer

Mark G McDonald

John W Galella

A high performance serial bus operating at multiple transmission rates is disclosed. The serial bus is able to automatically generate data response packets for return to a requesting node. The automatic packet generation uses the source and destination information to generate a return destination packet for directing the requested data to the request source destination. Since the bus network is capable of operating at several different transmission rates, the speed at which the data request packet was transmitted is used for retransmitting the data requested back to the source node requesting the data.

System for reformatting a response packet with speed code from a source

A computer system allows for a hardware structure to participate in the transmission of P1394 packets, which are comprised of command or data blocks from linked list structures in a system memory, is disclosed. The system is able to provide dynamic appending of these command or data blocks to the link list while they are being operated upon. This provides an efficient transaction layer operation, which minimizes signalling between the link list operator or control code, and other hardware features.

Method and system for dynamically appending a data block to a variable

Disclosed method and apparatus allow for balanced usage of resources in dual bus computing systems wherein: (1) principal resources of the system--including a processor, a local bus, local bus controls, and a memory subsystem--are contained in a single system unit (e.g. a card); (2) devices are coupled to the system unit and to each other through a device communications bus that is also accessible to the processor of the system unit; (3) the system processor is required to have principal access to the local bus, as a 'System Bus Master', for time critical functions such as memory refresh; and (4) the devices include one or more devices that are required to have controlling access to the resources of the system unit, and for that purpose are required to have controlling access to the local bus as Alternate Bus Master entities. The disclosed arrangement allows an Alternate Bus Master operating in a burst mode, in which several cycles of data transfer may occur consecutively, to have continuous access to the local bus after a single signal handshaking exchange with the local bus controls; subject to over-riding conditions which ensure timely accomplishment of the time critical functions controlled by the processor/System Bus Master. The over-riding conditions are detected by special logic that acts, when necessary, to interrupt Alternate Bus Master access to the local bus without affecting the state of connection between the respective Alternate Bus Master and the communications bus.

Providing alternate bus master with multiple cycles of bursting access

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Boca Raton, FL, United States of America

Rex E McCrary