Texas Instruments Corporation

United States of America As Represented by the Secretary of the Air Force

Rex Alan Naden

John Charles Linn

Gene D Lee

Terry Wayne Noe

Alvis D Stephenson, Jr

Richard T Tarrant

David M Lee

Hsiao-Yuan Li

An educational learning aid which obtains its procedural data via bar code or other indicia imprinted on the edge of detachable work book sheets. The aid holds the detachable sheet over a touch sensitive array of switches so that touching or marking of the sheet is sensed by the underlying switches in the aid. The correct content of the answers is communicated to the aid by a bar code or machine readable section either on a work sheet or on a second sheet. In this fashion the operator responds to printed material on the sheet and is verbally reinforced by the learning aid for correct answers. Preferably a running tally of the operator's correct responses is kept and he is informed at the end of the exercise of his score. This score is optionally printed upon the paper upon completion of the exercise.

Educational aid for use with workbook

A magnetic domain memory system is provided that includes magnetic domain data chips having a major-minor loop organization wherein the system may include data chips having one or more defective minor loops. An erasable non-volatile semiconductor memory device is provided to record locations of defective minor loops for each chip in the system. In order to update the defective minor loop locations when a data chip is replaced a random access memory is provided to store the present map of locations and substitute data designating the new defective minor loops. A method of replacing the map in the erasable non-volatile semiconductor memory is also disclosed. An array of binary one bit data in the form of '1' or '0' is stored in the non-volatile semiconductor memory to designate defective and operative minor loops.

Bubble redundancy map storage using non-volatile semiconductor memory

A magnetic bubble memory chip structure on which a plurality of magnetic bubble storage loops are provided for containing information data as represented by bubbles and voids and including a dedicated area on the chip for containing redundancy data as represented by a chain of bubbles and voids arranged in a predetermined manner to identify good and defective information data storage loops. The redundancy data-containing dedicated area of the chip comprises a plurality of redundancy data-containing storage loops of equal number to the information data-containing storage loops so as to correspond thereto in a one-on-one relationship, with the number of individual bit positions included in each information data-containing storage loop being significantly greater than the number of bit positions included in each individual redundancy data-containing storage loop. At least one bubble detector is included on the chip, being associated with the information data-containing bubble storage loops and the redundancy data-containing storage loops for receiving readout of information data and redundancy data in an alternating coordinated sequence with each bit of information data from a respective information data-containing storage loop being preceded by a bit of redundancy data from the corresponding redundancy data-containing storage loop which identifies whether the following bit of information data is from a good or a defective information data-containing storage loop. The output from the detector is operably controlled by appropriate logic circuitry for restricting the usable readout from the information data-containing bubble storage loops to data which is delivered from good storage loops as determined by the redundancy data imparted by respective redundancy data-containing storage loops.

Magnetic bubble memory chip with dedicated redundancy data section

A magnetic memory system is provided that includes magnetic domain data chips having a block replicate organization wherein the system may include data chips having one or more defective minor loops. A dedicated minor loop is provided on the chip to store a redundancy map for locating the defective minor loops. The dedicated minor loop also provides for storing a synchronization pattern for initializing the system by having each minor loop properly addressed for transferring magnetic domains. The dedicated loop can only be accessed by a separate swap pin preventing a write operation by the user thus preserving the data stored therein.

Magnetic bubble memory chip synchronization and redundancy

Method and apparatus for testing and setting the field strength of permanent magnets in a magnetic bubble domain chip module, wherein the final molded module is formed to contain a pair of longitudinal slots which run through the module on opposite sides thereof. The module is inserted, via said slots, onto conducting members of a magnetic bubble module testing apparatus. The conducting members effectively provide one turn coils on each side of the module. Current is induced in these coils in such a way as to either add to or subtract from the bias field provided for the magnetic bubble domain chip by the permanent magnets of the module. The module is tested to determine the upper and lower operating levels of the bias field for effective operation of the chip, and the device is remagnetized to set the bias field of the module in the center, or optimal point, of the bias margin.

Method and apparatus for testing and setting magnetic field strength of

An associative bubble memory apparatus utilizing a plurality of registers therein to provide a high total memory capacity and to provide data retrieval or correlation based upon content rather than the address of the data of interest.

Associative bubble memory apparatus

A magnetic domain memory system is provided that includes magnetic domain data chips having a major-minor loop organization wherein the system may include data chips having one or more defective minor loops. A programmable read-only memory (PROM) device is provided to permanently record locations of defective minor loops for each chip in the system. Logic circuitry is employed to inhibit transfer of magnetic domains into or out of a defective minor loop responsive to the data stored at each address location of the PROM. In one embodiment, each memory word location of the programmable read only memory denotes the number of minor loops between defective loops. In a different embodiment, each memory bit location of the programmable read only memory contains either a binary 1 or 0, depending upon whether the associated minor loop is operative or inoperative. In a further embodiment, a multiplex technique is described wherein parallel data lines provide access to a plurality of magnetic domain memory modules and a PROM is utilized to store the locations of all defective minor loops in the memory modules so as to prevent transfer of magnetic domains thereto.

Magnetic domain minor loop redundancy system

A packaging assembly for magnetic bubble chips comprising at least one module assembly board having a surface to which is secured in a substantially planar array a plurality of magnetic bubble chips for the storing and processing of information. First and second sets of terminals are located on opposed lateral edges of the module assembly board for the routing therethrough of information to and from the chips. First and second mounting boards are provided, each board having a set of receptacles for the soldering thereto of a corresponding set of the terminals. A first coil surrounds the module assembly board and is wound about an axis parallel to that of the plane of the chips for producing a magnetic field parallel thereto. A second coil surrounds the first coil and is wound about an axis perpendicular to that of the first coil and parallel to that of the plane of the chips for producing a magnetic field parallel thereto. A bias field source is positioned exterior to the second coil to produce a substantially constant magnetic field perpendicular to the plane of the chips. The first and second coils are excited to produce a rotating magnetic field parallel to the plane of the chips to control the movement of magnetic bubbles therein. Control components for the storage and processing of information in the chips are also provided. Convenient access to the chips may be gained by the sequential disassembly of the bias field source, the second coil, reheating the solder connection between the terminals and receptacles, and the first coil.

Magnetic bubble chip packaging assembly

A non-volatile digital memory is utilized to generate digital pulses for controlling memory operations of a magnetic domain memory system. Each word stored in the memory contains data corresponding to the desired control signals. The digital memory synchronizes the control pulses with the in-plane rotating magnetic field. During each rotation of the magnetic field, a binary counter sequentially addresses the words stored in the digital memory such that the outputs from the digital memory correspond to the desired control signals.

Timing control means for a magnetic domain memory

A magnetic bubble processor comprising components for causing the movement of magnetic bubbles and a single chip having a layer of magnetic material in which magnetic bubbles can be moved. The chip comprises an input circuit for conveying electrical data and instructions into the processor and a generator responsive to the input data and instructions for producing magnetic bubbles representing bits of information. Paths are provided on the chip for routing magnetic bubbles within the processor as well as a memory organization accessible for the storage and retrieval of magnetic bubble information. The chip also includes magnetic bubble logic for performing mathematical operations and for providing magnetic bubble output information representing the results thereof. Further, the chip includes a magnetic bubble decoder for deciphering information and providing magnetic bubble output signals determinative of operations the processor is to perform and a magnetic bubble circuit responsive to the decoder output signals for controlling the routing of magnetic bubble information along predetermined paths within the processor, the storage and retrieval of information in the memory, and for instructing the logic as to which mathematical or logical operations are to be performed. A magnetic bubble detector on the chip converts the output of the logic from magnetic bubble information into discrete processor electrical output signals. The converted information is conveyed out of the processor by an output circuit on the chip. Thus, complex programs involving mathematical and logical operations using magnetic bubble data and instructions may be performed on one chip with a minimum of external circuitry and control required.

Single chip magnetic bubble processor

A programmable bubble material arrangement employing a plurality of logic components for performing eight different possible logic and arithmetic operations on two applied serial digital data streams. Separately applied control signals in the form of bubbles are applied to the arrangement to selectively program the arrangement, as desired. The logic components include transient bubble switches, resident bubble switches, bubble generators, bubble annihilators, exclusive merge elements, disjoint crossover elements and delay elements. The operations selectively performed are: A + B, A .sym. B, AB, A plus B with carry, A + B, A .sym. B, AB, and A plus B with carry. The arrangement operates equally with data streams either loosely packed (data bubbles periodically placed in the stream) or tightly packed.

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Richardson, TX, United States of America

Rex Alan Naden