Marvell Israel (misl) Ltd.

Marvellworld Trade Ltd.

Marvell Semiconductor Israel Ltd.

Reuven Ecker

Ido Bourstein

Shimon Avitan

David Moshe

Erez Reches

Meir Hasko

Dan Lieberman

Yiftach Banai

Michael Moshe

Basma Abd-elrazek

Inbal Gal

Performance measuring circuitry, for determining relative operational performance attributes of different types of a class of semiconductor component disposed on a semiconductor die, includes a first oscillator circuit including a plurality of first circuit element modules having a first circuit topology. The first oscillator circuit provides a first performance indication indicative of a collective performance attribute of all types of components in the class. A second oscillator circuit separate from the first oscillator circuit includes a plurality of second circuit element modules having a second circuit topology, and provides a second performance indication responsive to different contributions from different types of components in the class. A comparison circuit receives outputs of the first and second oscillator circuits and determines the relative performance characteristic of the different types of components. Dice may be binned according to performance, for use in assembly of operational circuits with different performance characteristics.

Method and circuitry for semiconductor device performance characterization

An Integrated Circuit (IC) includes a memory, circuit interconnections and control logic. The memory includes multiple standard-library Static Random Access Memory (SRAM) cells disposed on a substrate of the IC in multiple first layers, so that access to a respective SRAM cell to read and write data is through a cell-interface. The circuit interconnections, fabricated in one or more second layers separate from the first layers, interconnect cell-interfaces of a subgroup of the SRAM cells to form a ring oscillator that includes a cascade of N stages defined by the interconnected SRAM cells. The control logic is coupled to the cell-interfaces via the circuit interconnections, and is configured to apply an input signal to one or more of the cell-interfaces so as to trigger an oscillation of the ring oscillator whose frequency of oscillation is indicative of a speed of the SRAM cells of the memory.

Ring oscillator built from SRAM cells interconnected via standard cell-interface

Aspects of the disclosure provide an amplifier system and a method for dynamically cancelling an offset voltage. The amplifier system includes a chopper amplifier system that includes a differential amplifier with an offset calibration circuit. The chopper amplifier system is configured to generate an output signal including voltage variations indicating an offset voltage of the differential amplifier. The amplifier system also includes a feedback circuit configured to determine a polarity of the offset voltage of the differential amplifier based on the output signal, and to transmit a control signal to the offset calibration circuit to reduce the offset voltage of the differential amplifier.

Filter-less chopping for offset cancellation

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a memory array, a ring oscillator and a speed determination circuit. The memory array is defined by a plurality of memory cells that are based on a memory cell design. The ring oscillator has a plurality of inversion stages formed of a plurality of modified memory cells based on the memory cell design. The speed determination circuit is configured to determine a speed of the ring oscillator.

Method and apparatus for memory speed characterization

Systems and methods are provided for a receiver device for receiving data signals from devices of disparate types. An amplifier is configured to receive a voltage reference signal and a data signal, the data signal being received from a device, the amplifier being configured to output an output signal based on a comparison of the data signal to the voltage reference signal. A voltage reference level shifter is configured to selectively level shift the voltage reference signal supplied to the amplifier based on a type of device with which the receiver is communicating. A data signal level shifter is configured to selectively level shift the data signal supplied to the amplifier based on the type of device with which the receiver is communicating.

Systems and methods for data receipt from devices of disparate types

Aspects of the disclosure provide an integrated circuit (IC). The IC includes an input interface and a controller. The input interface is configured to receive an input signal providing information for controlling a supply voltage based on a performance characteristic of another IC. The controller is configured to generate an output signal for controlling the supply voltage based on a combination of the input signal and a performance characteristic of the IC.

AVS master slave

Aspects of the disclosure provide an integrated circuit (IC) chip that includes a feedback control circuit and a detecting circuit. The feedback control circuit is configured to govern a feedback signal to a first regulator that regulates a first power supply to the IC chip based on the feedback signal. The feedback control circuit is powered at least partially by a second power supply. The detecting circuit is configured to detect a power down of the second power supply, and to cause the feedback control circuit to be disengaged from the feedback signal in response to the power down.

Method and apparatus for regulator control

An integrated circuit includes an operational circuit module receiving a supply voltage from a voltage regulator external to the integrated circuit, and an adaptive voltage scaling module to adjust the supply voltage based on performance characteristics of the operational circuit module. The adaptive voltage scaling module can include a performance monitoring module disposed on the integrated circuit and configured to generate at least an indicator corresponding to at least one performance characteristic of the operational circuit module. The adaptive scaling module can include a voltage requirement determination and voltage feedback generator module disposed on the integrated circuit and coupled to the performance monitoring module. The voltage requirement determination and voltage feedback generator module is configured to output a feedback voltage signal having a voltage level as a function of at least the indicator. The voltage regulator can regulate the supply voltage as a function of the feedback voltage signal.

AVS-adaptive voltage scaling

Aspects of the disclosure provide an integrated circuit having a delay element that is configured as a complementary voltage based current starved delay element. The delay element drives an output node to generate an output signal in response to an input signal received at an input node. The delay element includes a first switch transistor configured to switch on in response to the input signal satisfying a switching condition, and a second switch transistor configured to switch on in response to the input signal satisfying the switching condition. The first switch transistor drives the output node with a first current that is controlled by a first bias voltage. The second switch transistor drives the output node with a second current that is controlled by a second bias voltage. The first bias voltage and the second bias voltage are complementary. In an example, both the first switch transistor and the second switch transistor are NMOS transistors. In another example, both the first switch transistor and the second switch transistor are PMOS transistors.

Method and apparatus for generating delay

AVS&#x2014;adaptive voltage scaling

Aspects of the disclosure provide a method for reducing crosstalk effects. The method includes tracking data for output onto at least a first transmission line and a second transmission line, determining a combined pattern in a first signal and a second signal to be respectively transmitted by the first transmission line and the second transmission line, and setting a delay to transmit at least one of the first signal and the second signal as a function of the combined pattern.

Method and apparatus for reducing crosstalk effects

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first operational circuit module receiving a first supply voltage from a first voltage regulator that is external to the integrated circuit, and a first adaptive voltage scaling module to adjust the first supply voltage based on performance characteristics of the first operational circuit module. In an embodiment of the disclosure, the first adaptive voltage scaling module includes a first performance monitoring module. The performance monitoring module is disposed on the integrated circuit, and is configured to generate at least a first indicator corresponding to at least one performance characteristic of the first operational circuit module. Further, the first adaptive scaling module includes a first voltage requirement determination and voltage feedback generator module that is disposed on the integrated circuit, and is coupled to the first performance monitoring module. The first voltage requirement determination and voltage feedback generator module is configured to output a first feedback voltage signal having a voltage level that varies as a function of at least the first indicator. The first voltage regulator is configured to regulate the first supply voltage as a function of the first feedback voltage signal.

Aspects of the disclosure provide a method for calibrating pulse-width based measurement. The method includes generating a sloped time varying signal having a voltage level that varies with time, and generating a calibration pulse having a first calibration edge and a second calibration edge. The first calibration edge corresponds to a first calibration time that the sloped time varying signal has a first reference voltage, and the second calibration edge corresponds to a second calibration time that the sloped time varying signal has a second reference voltage. Further, the method includes modifying a parameter that governs a slope of the sloped time varying signal to calibrate the slope, such that a calibration pulse width of the calibration pulse is substantially equivalent to a reference time length. Then, the method includes performing pulse-width based measurement based on the calibrated slope.

Method and apparatus for calibration of pulse-width based measurement

A clock generator is disclosed that includes a lock detector. The lock detector is configured to generate a lock signal based on control signals of a phase lock loop circuit that generates an output clock of a desired frequency that is phase locked to a reference clock. The lock detector generates a mismatch signal based on a comparison between the phases of the reference clock and the output clock to generate a compare result. The lock detector delays the compare result by a time period Tand AND the delayed compare result with the compare result to generate the mismatch signal. The lock detector includes a lock-counter that counts a number of reference clock cycles when the mismatch signal remains at 0. The lock signal indicates that a lock-state is achieved when the number of counted reference clock cycles equals a set-value.

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Haifa, Israel

Reuven Ecker