Xilinx, Inc.

Reto Stamm

Ian L McEwen

Ciaran McGloin

Mary O'Connor

Stephen M Trimberger

Christopher H Kingsley

Bobby Yang

Jason J Moore

Jay T Young

Eric M Shiflet

John D Corbett

Teymour M Mansour

David A McNicholl

Christophe Brotelande

Andrew G Anderson

Donald Audley Staab

Phoumra Tan

A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaining arc usage strings against an already-tested arc file to identify the arc usage string (test pattern) having the greatest number of untested arcs. A test sequence list of test patterns ranked in order of the most number of untested arcs to the least number of untested arcs is provided to a tester and the IC is tested in order of the test patterns on the test sequence list.

Method and apparatus for testing programmable integrated circuits

A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.

Isolation verification within integrated circuits

A defect is automatically isolated in an integrated circuit device having programmable logic and interconnect circuits. A sequence of configurations is created to route data in a pattern through the programmable logic and interconnect circuits. Each configuration within the sequence is determined (e.g., generated or selected from a plurality of pre-generated configurations) as a function of output data from a prior configuration in the sequence. For each configuration in the sequence, the programmable logic and interconnect circuits are configured with the configuration and an automatic test instrument routes data in the pattern through the programmable logic and interconnect circuits. For each configuration in the sequence, the output data from the programmable logic and interconnect circuits is assessed. For each configuration in the sequence, the assessed output data isolates the defect to a portion of the pattern for the configuration that is within the portion for a prior configuration in the sequence.

Automatic isolation of a defect in a programmable logic device

The present invention includes an apparatus and method to optimize a set of test designs to obtain complete coverage while reducing bit stream size for programmable fabric. Test designs are selected that do not result in lost coverage. The method selects a set of test designs, removes the set of test designs, and then determines if coverage is lost. If coverage is lost, the method creates a new set of test designs to test the lost coverage. If the new set of test designs is smaller than the removed set, the new set of test designs is added to the test design suite; otherwise the removed test designs are added back to the test design suite. The decision to add the new test designs or removed test designs is based on a number of criteria including evaluating the number of uniquely tested resources in each test design.

Method and apparatus for reducing the number of test designs for device testing

Identification of a faulty net in a design implemented on a programmable logic device (PLD). In one approach, configuration data is generated to implement a duplicate circuit of a failing sub-circuit in the design. The PLD is configured with the configuration data that implements the failing sub-circuit and the duplicate circuit, and at least one set of input signals is applied to the sub-circuit and the duplicate circuit. A signal from each net in the sub-circuit is compared on the PLD to a corresponding net in the duplicate circuit. In response to the signal from the net in the sub-circuit being unequal to a signal from the corresponding net in the duplicate circuit, the net in the sub-circuit is identified as faulty.

Fault isolation in a programmable logic device

An electronic business card has a memory storing presentation slide images, a display that displays the images, and a processing device that governs the display process. The card has input devices (pads or buttons such as FORWARD, BACK and INDEX) allowing the user to control the display. The display's picture elements are preferably implemented as multi-chromic beads whose respective physical orientations are controlled by the processing device so as to form the viewed image. A method requires a target audience member to view at least one 'payload' image (information that a presenter desires to propagate among a target audience), in association with at least one 'hook' image (a quiz or game), on an electronic business card, PDA, or PC. The method includes presenting the payload image in association with the hook image, receiving and analyzing a user response, and displaying a reward image if the user response satisfies a criterion.

Arrangements enabling an audience to replay a presentation

A system and method for testing a parameterizable logic core are provided in various embodiments. A test controller is configured and arranged to generate a set of random parameter values for the logic core. A netlist is created from the parameterized logic core, and circuit behavior is simulated using the netlist. In other embodiments, selected parameter values are optionally weighted to increase the probability of generating those values, and the parameter set is cloned and mutated when simulation fails.

System and method for testing parameterized logic cores

A method and arrangement for executing instructions of a computer program using a programmable logic device to perform selected functions of the program. Profile data for code segments of the computer program are generated during program execution. Based on the profile data, a code segment is selected for transformation to a hardware implementation. The functionality of the selected code segment is transformed into a configuration bitstream, and the PLD is configured with the configuration bitstream. During program execution, the PLD is activated in lieu of executing the code segment.

Instruction processor and programmable logic device cooperative computing arrangement and method

A method and system for distributing by a server data processing system computing tasks for execution amongst a plurality of client data processing systems having different resource characteristics. Each task includes one or more subtasks, and each subtask has one or more resource requirements. Each of the clients requests from the server a subtask upon occurrence of a first event, for example, an idle machine. The server in response to a request from a client, selects a subtask for execution by the client as a function of the resource requirements of the subtask and the particular resource characteristics of the client.

Client-server task distribution system and method

A method and apparatus for testing software having a user interface are presented in various embodiments. The method generally entails evolving a test sequence by generating random test actions. A test sequence is created by assembling a set of interface components associated with an interface window. One of the interface components is randomly selected, and a random action is generated to apply to the interface component. The test sequence is documented by recording data that identifies the interface component and the action, and the action is then applied to the user interface.

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Sunnyvale, CA, United States of America

Reto Stamm