Micron Technology Incorporated

Mircon Technology, Inc.

Reshmi Basu

Jonathan Scott Parry

Richard Cameron Murphy

Giuseppe Cariello

Luca Porzio

Libo Wang

David Aaron Palmer

Christian M Gyllenskog

Roberto Izzi

Richard Donald Maes, Ii

Nitul Gohain

Michael Richard Ives

Katie Blomster Park

Gary A Johnson

William Leins Stube, Ii

Anthony Joseph Dupont

Robert J Pintar

Kishore Kumar Muchherla

Xiangang Luo

Carla L Christensen

Deping He

Daniel R Loughmiller

Stephen D Hanna

Chun Sum Yeung

Ryan G Fisher

Yanhua Bi

Jeffrey Scott McNeil, Jr

Arvin Daniel A Daguro

Noel Marquez

Kenneth Koenig

Methods, systems, and devices for dynamic status registers array are described. An apparatus may include one or more memory dice coupled with a data bus. The apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. The first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. The controller may further transmit second command to the first memory die to request a status of the first operation. The controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.

Dynamic status registers array

In some implementations, a memory device may receive a write command that includes data to be written to the memory device. The memory device may receive an indication that single-level cell data caching is deactivated for the data. The memory device may determine whether the data is associated with a first data type or a second data type. The memory device may selectively write the data to single-level cell cache memory or multi-level cell main memory based on a determination of whether the data is associated with the first data type or the second data type and a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.

Opportunistic storage of non-write-boosted data in write booster cache memory

Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.

Write booster pinning

Methods, systems, and devices for memory operations are described. A host system may obtain data for writing to a memory system. The host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. Based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. The memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. In other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.

Determining available resources for storing data

Methods, systems, and devices for storing parity during refresh operations are described. In some examples, refresh operations may be performed on a memory device when the memory device is idle. For example, a refresh operation may entail performing a logical operation on first data and a first set of parity bits and second data and a second set of parity bits. The logical operation may generate a third set of parity bits which may be used for data retention purposes. Moreover, during a read operation, the third set of parity bits may be used to recover corrupt or otherwise invalid data in the event of an error.

Storing parity during refresh operations

Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

Low-power boot-up for memory systems

Methods, systems, and apparatuses related to autonomous vehicle object detection are described. An autonomous vehicle can capture an image corresponding to an unknown object disposed within a sight line of the autonomous vehicle. Processing resources available to a plurality of memory devices associated with the autonomous vehicle can be reallocated in response to capturing the image and an operation involving the image corresponding to the unknown object to classify the unknown object can be performed using the reallocated processing resources.

Autonomous vehicle object detection

Methods, systems, and apparatuses related to autonomous vehicle object detection are described. A method can include receiving, by an autonomous vehicle, an indication that the autonomous vehicle has entered a network coverage zone generated by a base station and performing an operation to reallocate computing resources between a plurality of different types of memory devices associated with the autonomous vehicle in response to receiving the indication. The method can further include capturing, by the autonomous vehicle, data corresponding to an unknown object disposed within a sight line of the autonomous vehicle and performing, using the reallocated computing resources, an operation involving the data corresponding to the unknown object to classify the unknown object.

Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.

Host-based error correction

Methods, systems, and devices for adaptive throughput monitoring are described. In some examples, a memory system may be associated with one or more clocks that are each associated with a respective subcomponent. When the memory system receives a plurality of commands, the memory system may determine a throughput of the commands. Based on the determined throughput, the memory system may adjust a rate of one or more of the clocks.

Adaptive throughput monitoring

Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

Caching for multiple-level memory device

Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include determining a type of characteristic set for each of a plurality of memory objects to be written to a memory system. The memory system can include a first memory device and a second memory device. The method can further include configuring each of the plurality of memory objects to be written to the memory system in the first memory device or the second memory device based on the determination of the type of characteristic set associated with each of the plurality of memory objects. The method can further include writing each of the plurality of memory objects to the first memory device or the second memory device based on the configuration of each of the plurality of memory objects.

Object management in tiered memory systems

Methods, systems, and apparatuses related to management of a computing device usage profile are described. The usage profile can be a usage profile of a computing device. Characteristics of workloads executed by a computing device can be monitored to determine whether performance of the computing device can be optimized by execution of an updated usage profile. Responsive to a determination that the performance of the computing device can be improved by execution of an updated usage profile, the updated usage profile can be received by the computing device and executed thereon.

Management of a computing device usage profile

Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

Redundant array management techniques

A method includes performing a first operation to program data to a group of memory cells of a memory device, wherein the data comprises host data and a bit pattern indicative of a first temperature of the group of memory cells and receiving a signal to perform a second operation to read the host data from the group of memory cells. The method further includes determining, responsive to receipt of the signal, whether a second temperature of the group of memory cells is outside a threshold temperature differential that is based on the bit pattern indicative of the first temperature of the group of memory cells, applying a voltage offset signal to the group of memory cells responsive to a determination that the second temperature of the group of memory cells is outside the threshold temperature differential, and performing the second operation to read the host data from the group of memory cells subsequent to application of the voltage offset signal to the group of memory cells.

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Boise, ID, United States of America

Reshmi Basu