Intel Corporation

Reshma Pattan

Jasvinder Singh

Chris MacNamara

David Hunt

Declan W Doherty

Chris Macnamara

Harry Van Haaren

Mohammad Abdul Awal

Radu Nicolau

Examples include techniques for monitoring a data packet transfer rate at an interface queue, and based at least in part on a comparison of the data packet transfer rate to a threshold, assigning the interface queue from a core of a first class to a core of a second class or assigning the interface queue from a core of the second class to a core of the first class.

Dynamic traffic-aware interface queue switching among processor cores

Technologies for dynamic multi-core packet processing distribution include a compute device having a distributor core, a direct memory access (DMA) engine, and multiple worker cores. The distributor core writes work data to a distribution buffer. The work data is associated with a packet processing operation. The distributor core may perform a work distribution operation to generate the work data. The work data may be written to a private cache of the distributor core. The distributor core programs the DMA engine to copy the work data from the distribution buffer to a shadow buffer. The DMA engine may copy the work data from one cache line of a shared cache to another cache line of the shared cache. The worker cores access the work data in the shadow buffer. The worker cores may perform the packet processing operation with the work data. Other embodiments are described and claimed.

Technologies for dynamic multi-core network packet processing distribution

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Tuam, Ireland

Reshma Pattan