International Business Machines Corporation

Renzo Maccagnan

Philippe Coronel

Jean Canteloup

Edith Lattard

David Cruau

Francois Leverd

Jean-Phillippe Vassilakis

Phillipe Coronel

Stephane Thioliere

Frederic Lebrun

Christophe Girard

Philippe Lacombe

Eric Mass

There is disclosed a method of forming contacts and metal lands onto a semiconductor structure at the first level of metallization (M ). The initial structure is a silicon substrate having diffusion regions formed therein and a plurality of gate conductor stacks formed thereon. The structure is passivated by an insulating layer. Contact holes of a first type are etched in the insulating layer to expose some diffusion regions, then filled with doped polysilicon to form conductive studs substantially coplanar with the insulating layer surface. A first mask (M ) is formed at the surface of the structure to expose M land recess locations including above said studs. The masked structure is anisotropically dry etched to create M land recesses. Next, the M mask is removed. A second mask (CS) is formed at the surface of the structure to expose desired contact hole locations of a second type. The masked structure is again anisotropically dry etched to expose the diffusion regions and the top of gate conductor stacks. The CS mask is removed. Finally, said M land recesses and contact holes are filled with a metal, so that the metal and the insulating material top surface are substantially coplanar.

Method of forming first level of metallization in DRAM chips

The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the &ldquo;array&rdquo; and &ldquo;kerf&rdquo; areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the &ldquo;array&rdquo; areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the &ldquo;array&rdquo; areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the &ldquo;kerf&rdquo; areas. The polysilicon in these deep trenches is partially or totally removed by etching. Finally, the Si3N4 pad layer is eliminated, creating recesses that will be used as alignment marks for the subsequent photolithography steps. If the polysilicon is not etched, the above method will produce polysilicon bumps instead that can be used for the same purpose.

Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step

Method and system for real-time in-situ interactive supervision of a step performed in a tool during semiconductor wafer fabrication process. The system includes a tool and the computer attached thereto, an end point detection controller, a database and a supervisor to supervise the whole wafer processing for that step. The controller is used to monitor a key process parameter of the step and is adapted to perform in-situ measurements. The database contains the evolution of said process parameter in normal operating conditions and in all the identified deviations. It further contains the history of the wafer until this step and a reference to the batch and process names for this step and the wafer identification number. At the end of the step, the important process parameters and any alert code are stored in the database to up-date the wafer history. This technique allows a total clusterized wafer fabrication process and prevents wafer rejection.

Method and system for semiconductor wafer fabrication process real-time in-situ interactive supervision

A conventional initial deep trench structure consists of a patterned Si,N,pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO,collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO,is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO,is etched at least 6 times faster than the Si,N,(stopping on the Si,N,pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6&times; the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages. Next, N-type dopant is implanted in the upper portion of the silicon substrate to create a doped region. The trench is filled with a layer of doped polysilicon (POLY2) which is planarized by chemical-mechanical polishing down to approximately the Si,N,pad layer surface and finally recessed down to a depth level substantially coplanar with the silicon surface substrate to create a POLY2 stud. The buried strap is formed by the doped region and POLY2 stud. The above method presents significant advantages in terms of product reliability, throughput improvements and process flow simplification.

Method of forming buried straps in DRAMs

An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O,/CF,chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.

Method for buried plate formation in deep trench capacitors

The starting structure consists of a silicon substrate having diffused regions formed therein and gate conductor stacks formed thereupon that is passivated by a TEOS layer as standard. At a further stage of the wafer fabrication process, contact holes exposing some diffused regions and top of gate conductor stacks have been formed. At least one contact hole exposing a diffused region has been filled with doped polysilicon and the structure has been coated with a layer of an anti-reflective material (ARC) then, with a patterned mask to expose the ARC layer at the contact holes locations. The process improvement essentially consists in the use of a non selective chemistry which etches the doped polysilicon, the ARC and TEOS materials at substantially the same rate in a RIE etcher. A NF3/CHF3 gas mixture with a 23/77 ratio is adequate in that respect. The etch time duration is controlled first by an optical etch end-point detection system adapted to detect the signal transition at the TEOS layer exposure and then by an interferometric etch endpoint detection system to monitor the etched thickness to accurately stop when the selected depth for the M0 land recesses is reached. Finally, said recesses are filled with a metal (e.g. tungsten) as standard to produce the desired M0 metal lands.

Method of forming metal lands at the M0 level with a non selective chemistry

In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. The storage capacitor is formed in a trench etch in a silicon substrate which is partially filled with polysilicon. The substrate is conformally coated by a TEOS SiO.sub.2 collar layer having a non-uniform thickness. A chemistry having a high TEOS SiO.sub.2 /Si3N.sub.4 and polysilicon selectively (i.e. which etches TEOS SiO.sub.2 faster than Si.sub.3 N.sub.4 and polysilicon by a factor of at least 6) is used to anisotropically etch the collar layer. C.sub.4 F.sub.8 /Ar/C) mixtures which have selectivities of 9:1 and 15:1 are adequate. When the surface of the Si.sub.3 N.sub.4 pad layer is reached (this can be accurately detected), the etch is continued a short period of time to ensure the complete removal of the horizontal portions of the collar layer, including at the trench bottom, but not the vertical portions in the trench sidewalls.

Collar etch method to improve polysilicon strap integrity in DRAM chips

According to the present invention, there is disclosed a method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches according to a planarization main step which is comprised of three processing steps. The starting structure (10) consists of a silicon substrate (11) coated by a patterned Si.sub.3 N.sub.4 layer (12) which delineates shallow trenches (20A, 20B) with a conformal layer (22) of TEOS SiO.sub.2 formed thereon. A planarizing medium, typically two superimposed photoresist layers (24.25) is formed onto the resulting structure to provide a substantially planar surface. At this stage of the fabrication, the structure is standard. Now, this planar surface is translated by a non selective two-steps plasma etching in the TEOS SiO.sub.2 layer (22). Next, should some photoresist material remain onto the structure it would be removed. Finally, a highly selective TEOS SiO.sub.2 /Si.sub.3 N.sub.4 RIE etching step is performed which stops on the Si.sub.3 N.sub.4 layer. The preferred chemistry is C.sub.4 F.sub.8 /Ar or C.sub.4 F.sub.8 /CO/Ar mixture. There is no longer the notion of process window because both the 'silicon polish' and 'Si.sub.3 N.sub.4 pad residuals' type of defects are eliminated. The present method offers significant advantages in terms of final test yield improvement, cost reduction and reproducibility.

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Villabe, France

Renzo Maccagnan