Altera Corporation

Alter Corporation

Renxin Xia

Keith Duwel

Kerry S Veenstra

Juju Joyce

Nitin Prasad

David Wolk Mendel

Marwan A Khalaf

Juin-Yeu Lu

Yi Gao

Mukunda Krishnappa

Juju Chacko Joyce

A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

Apparatus and methods for communicating with programmable devices

Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter.

Method and system for partial reconfiguration simulation

Systems and methods for flexibly configuring one or more intellectual property (IP) blocks of a programmable logic device are described. The methods include configuring and operating a first portion of the programmable logic device before configuring a remaining portion of the programmable logic device. By operating the first portion before configuring the remaining portions, various timing constraints including power-up timing constraints can be met by the programmable logic device.

Systems and methods for flexibly configuring a programmable logic device

Apparatus and methods for communicating with programmable logic devices

Techniques for actively configuring a programmable circuit using configuration data stored in an external memory are provided. The programmable circuit attempts to read a device identification code from an external memory device using a read instruction. The programmable circuit then attempts to identify the external memory device by matching the identification code returned from the external memory with a code in a first predefined list. A match indicates that the programmable circuit has hardware that can generate instructions that the memory device can recognize. After the programmable circuit identifies the memory device, the programmable circuit sends instructions to the external memory device according to a predefined protocol understood by the memory device. The programmable circuit can also compare a device identification code for a particular memory device with a second list of identification codes to determine whether a user wants the programmable circuit to support that memory device.

Techniques for actively configuring programmable circuits using external memory

A programmable logic device (PLD) includes configuration circuitry. The configuration circuitry is adapted to receive serial configuration data from a configuration device. The configuration circuitry is further adapted to program a function of the PLD without using an input buffer to store the configuration data.

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San Jose, CA, United States of America

Renxin Xia