Motorola Corporation

Renwin J Yee

Thomas D Petty

Troy L Stockstad

Jefferson W Hall

Robert L Vyne

Gary L Spraggins

William B Newton

Martin J Abresch

Bradley T Moore

Stuart Ellner

Laurel L Hoekstra

Eric A Ramsland

A battery charge control circuit (10) senses the charge condition of cells in a battery pack (12, 14, 16, 18) using a measurement circuit (51). Upon detection of a single under-voltage cell, the charge control circuit is placed in a sleep mode. Pack sense circuit (240) senses when the battery pack is placed in a charger. If circuit (10) was in a sleep mode, it is awakened. If any cell is measured over-voltage, the status is checked versus the other cells. If all the cells are over-voltage, the battery is considered balanced. If one or more cells are not over-voltage, a control circuit (32) activates a discharge transistor (212, 214, 216, 218), discharging the cell within a hysteresis voltage below the over-voltage limit. Charge balancing of cells is continued until the cells are within a programmable hysteresis voltage of each other.

Circuit and method for battery charge control

A resistor structure (10) having a heating element (35) and a resistor (32), and a method of trimming the resistor (32). The heating element (35) is separated from the resistor (32) by a layer of dielectric material (19). The resistor (32) has a layer of resistive material (23) on an etch control layer (22). The resistor (32) is trimmed by providing current pulses (62) through the heating element (35). Heat generated by the current pulses flows to the resistor (32) and anneals or trims the resistor (32). A resistor trimming variable, e.g. a voltage across resistor contacts (30, 31), is monitored and the current pulses are modulated in accordance with the value of the resistor trimming variable (63). The trimming step is terminated when the desired resistance value of the resistor (32) is attained.

Resistor structure and integrated circuit

A battery monitoring circuit (10) sequentially samples individual voltages across a string of serially coupled battery cells (12-18). A control circuit (32) controls first and second multiplexers (34,42) to sample each battery voltage for an over-voltage condition. A comparator (52) detects an over-voltage condition by comparing a divided down battery voltage against a reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (26) in the battery cell conduction path. The battery cells are further sequentially sampled for an under-voltage fault. The comparator detects an under-voltage condition by comparing a second divided down battery voltage against the reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (24) in the battery cell conduction path.

Circuit and method of monitoring battery cells

Resistor structure and method of setting a resistance value

A pulsed battery charger circuit (11) for charging a battery (28). A control circuit (17) is responsive to a sense circuit (16) that monitors the battery voltage. The control circuit (17) pulses a first current source (25) or a second current source (20). An amplifier (14) is responsive to the first (25) and second (20) current sources for generating first and second predetermined voltages between a drive output (12) and a sense input (13). The first current source (25) is pulsed when the sense circuit (16) senses the battery voltage to be less than a first threshold voltage. The second current source (20) is pulsed when the sense circuit (16) senses the battery voltage to be greater than the first threshold voltage. Both the first (25) and second (20) current sources are disabled when the sense circuit (16) senses the battery voltage to be greater than a second threshold voltage.

Pulsed battery charger circuit

A battery charger status monitor circuit (40) for monitoring the status of a battery (12) charged with current pulses. The current pulses charging the battery (12) are reduced in frequency and duty cycle as the battery approaches a fully charged condition. By monitoring the number of current pulses charging the battery within a predetermined time period, the charge status of the battery (12) is determined. If no pulses are detected within the predetermined time period, the battery (12) is fully charged. A counter (47) is incremented by a clock signal. A charge signal resets the counter (47). The charge signal corresponds to the current pulses charging the battery. If the counter (47) reaches a predetermined count, the clock and charge signals are disabled. Reaching the predetermined count before resetting indicates the battery (12) is fully charged. When the counter is below the predetermined count, the battery (12) is being charged.

Battery charger status monitor circuit and method therefor

An operational amplifier enhances its negative slew rate by providing more base current to a bottom PNP output drive transistor. A large signal applied at the inverting input of the operational amplifier unbalances the differential input stage and provides maximum current through a current mirror circuit to the base of the PNP output transistor. A transistor is biased on by sufficient current flow through the current mirror circuit to draw even more base current from the base of the PNP output transistor and thereby enhance its negative slew rate.

Negative slew rate enhancement circuit for an operational amplifier

A monolithic operational amplifier (10) having an Miller loop compensation network (13) with improved capacitive drive. The monolithic operational amplifier (10) has an input stage (11), an output stage (12), and a compensation network (13). The compensation network (13) provides negative feedback between an output node (19) of the output stage (12) and an input node (16) of the output stage (12). The compensation network (13) has a compensation capacitor (26), a resistor (27), an isolation resistor (33), a shunt capacitor (28), and an isolation transistor (25). The compensation network (13) creates a dominant pole, a zero and a nondominant pole having a higher frequency than the zero. The nondominant pole improves a gain margin while preserving sufficient phase margin. The isolation transistor (25) provides improved capacitive drive.

Miller loop compensation network with capacitive drive

Leakage current is reduced in a piezoresistive transducer by forming a leakage barrier around a piezoresistive element of a piezoresistive transducer. The leakage barrier prevents the formation of a parasitic leakage path in the substrate thereby reducing the leakage current flowing through sections of the piezoresistive element, and stabilizing the resistance value and the output voltage of the piezoresistive transducer.

Piezoresistive transducer with low drift output voltage

A semiconductor membrane is fabricated in a substrate by applying a voltage to a Schottky diode or a capacitor formed on a surface of the substrate to create a depletion region in the substrate. The substrate is exposed to an electrochemical, anisotropic etch solution. Etching terminates at the depletion region, thus forming a membrane having a thickness defined by the thickness of the depletion region.

Growing community of inventors

Chandler, AZ, United States of America

Renwin J Yee