Qualcomm Incorporated

Renukprasad Hiremath

Satyanarayana Sahu

Xiangdong Chen

Radhika Vinayak Guttal

Venugopal Boynapalli

Animesh Datta

Ohsang Kwon

Hyeokjin Lim

Foua Vang

Qi Ye

Divya Gangadharan

Chih-Iung Kao

In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

High performance cell design in a technology with high density metal routing

Hybrid diffusion standard library cells, and related systems and methods are disclosed. The hybrid diffusion standard library cells may be fabricated with reduced costs because masks corresponding to fixed base layers remain constant across integrated circuit (IC) devices. In one aspect, a hybrid diffusion standard library cell is provided. The hybrid diffusion standard library cell employs multiple diffusion regions, wherein a break region separates at least two of the multiple diffusion regions. The hybrid diffusion standard library cell includes one or more MEOL interconnects at fixed locations that are configured to connect transistors to a first metal layer. The hybrid diffusion standard library cell includes at least one transistor. Including the break region between multiple diffusion regions helps to limit the locations of the fixed MEOL interconnects, which limits possible locations for base level transistors and fixes the base layer design.

Hybrid diffusion standard library cells, and related systems and methods

A MOS device for reducing an antenna effect is provided. The MOS device includes a diode including a first nMOS transistor having a first nMOS transistor source, a first nMOS transistor drain, a first nMOS transistor gate, and an nMOS transistor body. The nMOS transistor body is coupled to a first voltage source and is an anode of the diode. The first nMOS transistor source, the first nMOS transistor drain, and the first nMOS transistor gate are coupled together and are a cathode of the diode. The MOS device further includes an interconnect extending between a driver output and a load input. The interconnect is coupled to the cathode of the diode. The interconnect may extend on one metal layer only between the driver output and the load input.

Circuit and layout for a high density antenna protection diode

A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Digital circuit design with semi-continuous diffusion standard cell

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San Diego, CA, United States of America

Renukprasad Hiremath