Sun Microsystems, Inc.

Renu Raman

Joseph I Chamdani

Gajendra Prasad Singh

Rabin Sugumar

Ronald J Melanson

Greg Papadopoulos

A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal. The apparatus further provides means for generating intermediary signals within a control block and then generating output signals to a data storage block. The apparatus also involves generating timing signals to a plurality of flip-flops dependent upon the behavior of the multi-function signal.

Thread switch circuit design and signal encoding for vertical threading

A random access memory includes a first memory bank, a second memory bank, an error checking circuit operatively connected to receive data read from the first memory bank, and a multiplexer operatively connected to input data read from both the first memory bank and the second memory bank, wherein input selection of the multiplexer is controlled by an output of the error checking circuit. A method for reducing errors in a memory system includes writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus. A method for reducing errors in a memory system comprises writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus.

Partitioned random access memory

A vertical multi-threading processor includes one or more execution pipelines that are formed from a plurality of multiple-bit pipeline register flip-flops. The multiple-bit pipeline register flip-flops supply multiple storage bits. The individual bits of a multiple-bit pipeline register flip-flop store data for one of respective multiple threads or processes. When an executing (first) process stalls due to a stall condition, for example a cache miss, an active bit of the multiple-bit register flip-flop is stalled, removed from activity on the pipeline, and a previously inactive bit becomes active for executing a previously inactive (second) process. All states of the stalled first process are preserved in a temporarily inactive bit of the individual multiple-bit register flip-flop in each pipeline stage.

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Los Altos, CA, United States of America

Renu Raman