Synopsys, Inc.

Renu Mehra

Sabyasachi Das

James David Sproch

Kaushik De

KunMing Ho

Ben Mathew

Vikram Saxena

Michael M&uuml;nch

Bernd Wurth

Michael Munch

Godwin R Maben

David Allen

Jin Wu

Meera Viswanath

In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff checks.

Low-power static signoff verification from within an implementation tool

A system to generate a design of an integrated circuit, the system comprising a memory and a processor, the processor to define a plurality of voltage area regions (VARs), based on an availability of one or more of a primary power source and one or more secondary power sources. The processor further to constrain placement and/or routing of an element in the design of the integrated circuit within a voltage area region of the plurality of voltage area regions defined by secondary power/ground (PG) constraints based on power requirements of the element.

Method to perform secondary-PG aware buffering in IC design flow

The present invention facilitates relatively accurate power consumption estimates performed at the register transfer level for scaleable circuits with similar architectural characteristics and features. A power evaluation process of the present invention includes a critical path delay based macro energy model creation process and a scaleable power consumption estimation process. In one embodiment of the present invention, the critical path delay based macro energy model creation process provides a base macro energy table and scaling functions (e.g., a bit width scaling function and a normalizing period scaling function). The scaleable power consumption estimation process utilizes the base macro energy table and scaling functions to estimate power consumption of a circuit. The base energy macro table comprises energy values that are based upon a critical path delay period and correspond to normalized toggle rates. Different bit width circuit toggle rates are converted to normalized toggle rates based upon time periods derived from a normalizing period scaling function. The normalized rates are utilized to lookup an energy per event value that is then scaled in accordance with a bit width scaling function of the present invention. The bit width scaling function is a polynomial function based upon a least square error analysis of sample bit width power consumption values corresponding to average characteristic parameters multiplied by a critical path normalization value (e.g., 1.2 times the critical path delay). The scaled energy per event value is divided by the critical path normalization value to provide an power consumption estimate for a particular bit width.

System and method for estimating power consumption of a circuit thourgh the use of an energy macro table

A method and system for power savings within a pipelined design by performing intelligent stage gating. The present invention recognizes that not every operand applied to the input of a pipeline requires a recomputation in the different pipeline stages. Circuitry is used to generate a signal, C, indicating that this condition holds. C is then used to gate the register bank at the input of the first pipeline stage thereby potentially saving power in the register bank. Moreover, C can also be stored in a register, the output of which: a) gates the register bank of the second stage; and b) connects to another register to store signal C to be used in the third stage. Power savings is provided by not clocking the register circuit of the stage, and in some instances, power is saved within the stage's associated combinational logic. In one embodiment, a register (to store C) is added in each stage of a pipeline to use C as a gating signal in the subsequent stage. This yields a structure in which signal C propagates through the pipeline in synchronization with the clock, successively gating the associated register banks. The value of C is generated whenever the output of the stage is inconsequential. For example, the output can be inconsequential in cases when duplicate operands are received in back-to-back clock cycles. Also, in maximum and minimum cases a operand that is not larger or smaller, respectively, than the largest or smallest previously received operand can yield an inconsequential result.

Method and system for pipe stage gating within an operating pipelined circuit for power savings

A computer-implemented process for determining a signal function for use in controlling the application of signal operands to a circuit-implemented function for the purpose of power reduction. The present invention receives a netlist represented as a graph data structure having nodes interconnected with signal lines. A node can have one output (single fan-out) or can have more than one output (multiple fan-outs). Termination points of the graph are identified as inputs to registers or primary outputs. From the termination points, and using a breadth-first traversal process, the present invention traverses each node of the netlist. A parent node is not processed in the breadth-first traversal until all of its child nodes have been processed. During traversal, an activation signal function is constructed for each input of a node. If the node has multiple outputs then a disjunctive Boolean expression is used, otherwise a conjunctive Boolean expression is used to determine the activation signal function. Activation signal circuitry is then added to each node if the power savings meet certain specified area and timing considerations. Selected nodes have operand isolation circuitry added thereto to implement the activation signal functions. The activation signal circuitry is used to gate the operand signal inputs to the node thereby saving power when the node's output is ignored.

Method and system for determining a signal that controls the application

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Sunnyvale, CA, United States of America

Renu Mehra