Motorola Corporation

Renny Lee Eisele

Ruey J Yu

Paul William Hollis

Daniel M McCarthy

A method and circuit for optimally controlling memory array bit line precharge timing to increase memory frequency of operation by generating a precharge output (110) for memory array bit lines in response to the earliest asserted control input among precharge control inputs. A write precharge signal (218) early enables a write precharge operation by enabling the precharge signal (110) a delayed period after an enabling falling dock edge of clock (104), as indicated by a write precharge enable signal (210), and during a write cycle, as indicated by a write precharge trigger (212). Thereafter, a default precharge trigger (216) is enabled to ensure that write precharging operation continues for an extended and optimal duration. A read precharge trigger (214) enables precharging after a read operation by enabling the precharge signal (110) in close proximity to the disabling of read sense amplifiers within the memory array to enhance post-read precharging. Thereafter, the default precharge trigger (216), is enabled to ensure that the read precharging operation continues for an extended and optimal duration.

Method and circuit for controlling a precharge cycle of a memory device

Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing have the same timing as actual memory accesses have during functional mode operation. Thus delay testing during SCAN Mode through paths containing both combinational logic and memory arrays accurately determines path delays.

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Austin, TX, United States of America

Renny Lee Eisele