Intel Corporation

Renju Thomas

Jared Warner Stark, Iv

Chris Wilkerson

Andrew Thomas Forsyth

Jean-Luc Duprat

A processor includes an execution pipeline having one or more execution units to execute instructions and a branch prediction unit coupled to the execution units. The branch prediction unit includes a branch history table to store prior branch predictions, a branch predictor, in response to a conditional branch instruction, to predict a branch target address of the conditional branch instruction based on the branch history table, and address match logic to compare the predicted branch target address with an address of a next instruction executed immediately following the conditional branch instruction. The address match logic is to cause the execution pipeline to be flushed if the predicted branch target address does not match the address of the next instruction to be executed.

Dynamic branch hints using branches-to-nowhere conditional branch

Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.

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College Park, MD, United States of America

Renju Thomas