Indian Institute of Science

Centre for Development of Advanced Computing (c-dac)

Renji Varghese Chacko

Vinod John

Anurag Singh

Subhash Joshi Tharayparambil George

Akhila Elappully Manikandan

Seena Somarajan

Present disclosure discloses a simple litz planar architecture using minimal vias for reducing Alternating Current (AC) resistance. The simple litz planar structure comprises a plurality of conductor strands of a first layer, a plurality of conductor strands of a second layer; and a plurality of vias set. The first layer and the second layer are separated by an insulating layer and each vias set is configured to perform transposition between a corresponding conductor strand of the first layer and a conductor strand of the second layer. The disclosed transposition method is simple, easy to manufacture and consequently, cost effective. The reduction in AC resistance obtained using disclosed simple litz planar structure is similar to planar litz winding. Further reduction in AC resistance is obtained by implementing multi-transposition per layer in the disclosed simple litz winding structure.

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Kerala, India

Renji Varghese Chacko