Hitachi, Ltd.

Elpida Memory, Inc.

Renichi Yamada

Yoshinobu Kimura

Yuki Mori

Hiroya Ohta

Natsuki Tsuno

Toshiyuki Ohno

Kenichi Takeda

Shinichiro Kimura

Hiroshi Miki

Shuichi Tsukada

Takashi Ogawa

Kiyonori Oyu

Junichi Sakano

Hirotaka Hamamura

Kimihisa Furukawa

Tomoko Sekiguchi

Hiroyuki Okino

Kikuo Watanabe

A diagnostic system for a power conversion apparatus including a semiconductor device and performing a switching operation for carrying and interrupting a main current to a main current is disclosed. This system includes a trigger circuit that acquires reference time for the switching operation; and a delay time calculation circuit that acquires first time at which the main current takes a first main current set value and second time at which the main current takes a second main current set value, and that detects numerical data about a difference between the first time and the reference time and numerical data about a difference between the second time and the reference time.

Diagnosis system for power conversion device, diagnosis method for semiconductor module, and power conversion device

Provided are an inspection device that detects with high precision and classifies surface unevenness, step batching, penetrating blade-shaped dislocations, penetrating spiral dislocations, basal plane dislocations, and stacking defects formed in an SiC substrate and an epitaxial layer; and a system. In the inspection device using charged particle beams, a device is used that has an electrode provided between a sample and an objective lens, the device applies a positive or negative voltage to the electrode and obtains images. A secondary electron emission rate is measured and energy EL and EH for the charged particles are found. A first image is obtained using the EH and positive potential conditions. A second image is obtained using the EL and negative potential conditions. A third image is obtained at the same position as the second image, and by using the EL and positive potential conditions.

Semiconductor inspection device including a counter electrode with adjustable potentials used to obtain images for detection of defects, and inspection method using charged particle beam

In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.

Semiconductor inspection method, semiconductor inspection device and manufacturing method of semiconductor element

The present invention enables screening of the so-called variable retention time (VRT) failure, namely a retention failure occurring in a DRAM due to fluctuation of a data retention time like a random telegraph noise. A pause/refresh test for checking a data retention function is repeated at all memory cells of a chip so that memory cells at which the retention failure due to random fluctuation of the data retention capability over time may occur is subjected to screening.

Dynamic random access memories and method for testing performance of the same

Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.

Semiconductor device and manufacturing method thereof

Growing community of inventors

Tokyo, Japan

Renichi Yamada