International Business Machines Corporation

Rene Mueller

Vijayshankar Raman

Guy Maring Lohman

Ippokratis Pandis

Ronald Jason Barber

Yinan Li

Richard Sefton Sidle

Pinar Tozun

Tim Kaldewey

Evangelia Sitaridi

Adam J Storm

Christian Marcelo Garcia-Arellano

Ronen Grosman

Yuanyuan Tian

Robert S Germain

Chandrasekaran Mohan

Hui-I Hsiao

Bin He

Ru Fang

One embodiment provides for a method including performing, by a processing thread, a process that analyzes transactional operations by maintaining the transactional operations in transaction local side logs, and waiting until a successful transaction commit to append the transaction local side logs to a log stream. The processing thread processes the transactional operations on a key used to determine whether existing data is found for the key. The transactional operations are sped up through parallelism based on partitioning tables across nodes handling the transactional operations. A first process is performed by a first processor that processes updates for values of a key based on updating a first start time table index using unique keys and a start time field of a row for a first appearance of each unique key from the transactional operations.

Resolving versions in an append-only large-scale data store in distributed data management systems

One embodiment provides for a method including processing transactional operations on a key used to determine whether existing data is found for that key. A first time index is updated using unique keys and a start time field of a first appearance of each key from the transactional operations. A deferred update of prior versions of the key is performed for non-recent data upon determining that recent data in the transactional operations is found for the key.

One embodiment provides a method comprising receiving an input data stream, partitioning the input data stream into a plurality of data blocks, and compressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to compress. The processor sets compress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in compressing an assigned data block to exploit intra-block parallelism. The method further comprises writing a plurality of compressed data blocks resulting from the compressing to a storage device in encoded form.

Parallel Lempel-Ziv compression for highly-parallel computer architectures

One embodiment provides a method comprising adjusting a runtime of a dataflow processing environment to operate on multiple batches of objects. The method further comprises pre-allocating one or more vectors of objects, and processing the multiple batches one at a time. The one or more vectors of objects are re-used during processing of each batch.

Efficient dataflow processing for objects

One embodiment provides a method for transparent partial object instantiation for object oriented applications including analyzing, by a processor, application code to determine a list of objects. The processor determines a list of accessed fields for each of the objects based on performing analysis for each function in the application code for accessed fields and other functions invoked.

Partial object instantiation for object oriented applications

A method of orchestrated shuffling of data in a non-uniform memory access device including a plurality of processing nodes that connected by interconnects. The method includes running an application on a plurality of threads executing on the plurality of processing nodes. Data to be shuffled is identified from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and for simultaneously transmitting data over different interconnects to a plurality of different target processing nodes from a plurality of different source processing nodes. The data is shuffled among all of the memory devices based on the plan and each processing node is capable of accessing data from first and second local memory devices.

Data shuffling in a non-uniform memory access device

One embodiment provides a method comprising receiving a plurality of encoded and compressed data blocks, decoding the data blocks, and decompressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to decompress. The processor sets decompress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in decompressing an assigned data block to exploit intra-block parallelism. The method further comprises generating a final uncompressed output sequence based on uncompressed data blocks resulting from the decompressing.

Parallel Lempel-Ziv decompression for highly-parallel computer architectures

A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes that are connected by interconnects. The method includes running an application on a plurality of threads executing on the plurality of processing nodes. Data to be shuffled is identified from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and for simultaneously transmitting data over different interconnects to a plurality of different target processing nodes from a plurality of different source processing nodes. The data is shuffled among all of the memory devices based on the plan. The data includes operand data and operational state data of the source threads.

A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes connected by interconnects. The method includes running an application on a plurality of threads executing on the plurality of processing nodes. Data to be shuffled is identified from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and for simultaneously transmitting data over different interconnects to a plurality of different target processing nodes from a plurality of different source processing nodes. The data is shuffled among all of the memory devices based on the plan. Shifting the data-shifting table includes rotating a first ring with respect to a second ring.

Embodiments relate to data shuffling by logically rotating processing nodes. The nodes are logically arranged in a two or three dimensional matrix. Every time two of the nodes in adjacent rows of the matrix are aligned, adjacent nodes exchange data. The positional alignment is a logical alignment of the nodes. The nodes are logically arranged and rotated, and data is exchanged in response to the logical rotation.

Logical data shuffling

A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes that are connected by interconnects. The method includes running an application on a plurality of threads executing on the plurality of processing nodes. Data to be shuffled is identified from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and for simultaneously transmitting data over different interconnects to a plurality of different target processing nodes from a plurality of different source processing nodes. The data is shuffled among all of the memory devices based on the plan.

Described herein are techniques for supporting bi-temporal data in a key value cache system. An embodiment provides bi-temporal data as the basic functionality of a key value cache system. An embodiment provides a redesign of the core data structures of a key value cache system, adds bi-temporal data storage in the key value hashing structure, and provides a temporality-aware memory space manager. Embodiments can achieve the same performance as current key value cache systems for regular queries (that is, the queries that only access the current versions of data) while supporting bi-temporal data.

Bi-temporal key value cache system

Embodiments relate to data shuffling by logically rotating processing nodes. The nodes are logically arranged in a two or three dimensional matrix. Every time two of the nodes in adjacent rows of the matrix are positionally aligned, these adjacent nodes exchange data. The positional alignment is a logical alignment of the nodes. The nodes are logically arranged and rotated, and data is exchanged in response to the logical rotation.

A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes includes running an application on a plurality of threads executing on the plurality of processing nodes and identifying data to be shuffled from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and shuffling the data among all of the memory devices based on the plan.

Growing community of inventors

San Jose, CA, United States of America

Rene Mueller