U.S. Philips Corporation

Rene G Penning De Vries

Leonardus J Van Roozendaal

A semiconductor device (1) includes a circuit having at least one transistor Tr1 and first and second electrodes (30) and (32). A protection element (20) having a device region (21) forming a pn junction (23) within the semiconductor body (10) and covered by an electrode layer (21c) is connected via an electrode (27) to one (30) of the first and second electrodes for providing a conductive path between the first and second electrodes (30) and (32) when a voltage above a threshold voltage is applied to the first electrode (30). The electrode layer (21c) forms with at least part (21a) of the device region (21) a potential barrier (B) for causing the conductive path provided by the protection element (20) to pass from the electrode (27) to the pn junction (23) at least partly via the device region (21) of the protection element (20) thereby increasing the resistance of the path to the pn junction (23).

ESD protection element for CMOS integrated circuit

Method of manufacturing a semiconductor device in which a first conductive, aluminium containing layer (15) is deposited with a low step coverage process over an insulating layer (11) with contact openings (12), in which a second conductive layer (16) is deposited with a high step coverage so as to fill depressed parts of the first conductive layer at the area of the contact openings. The second conductive layer (16) then is substantially eliminated outside the depressed parts and interconnection lines (18) are formed in the first conductive layer. According to the invention the second conductive layer is deposited by D.C. bias sputtering of an aluminium alloy at a substrate temperature which is sufficiently high to obtain a sufficient surface mobility of the deposited alloy. Therefore a planarized layer of the second conductive material (18) is obtained.

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Eindhoven, Netherlands

Rene G Penning De Vries