Freescale Semiconductor,inc.

Semiconductor Components Industries, LLC

Nxp Usa, Inc.

Rene Escoffier

Jean Michel Reynes

Beatrice Bernoux

Evgueniy Nikolov Stefanov

Ivana Deram

Pierre Jalbaud

Francine Y Robb

Peter J Zdebel

Jeffrey Pearse

A transistor power switch device comprising an array of vertical transistor elements for carrying current between first and second faces of a semiconductor body. The device also comprises a semiconductor monitor element comprising first and second semiconductor monitor regions in the semiconductor body and a monitor conductive layer distinct from the current carrying conductive layer of the transistor array. The semiconductor monitor element presents semiconductor properties representative of the transistor array. Characteristics of the semiconductor monitor element are measured as representative of characteristics of the transistor array. Source metal ageing of a transistor power switch device is monitored by measuring and recording a parameter which is a function of a sheet resistance of the monitor conductive layer when the transistor power switch device is new and comparing it with its value after operation of the device. A measured current is applied between a first location on an elongate strip element of the monitor conductive layer and a first location on one of a pair of lateral extensions of the strip, and the corresponding voltage developed between a second location on the elongate strip element and the other of said pair of lateral extensions is measured.

Transistor power switch device and method of measuring its characteristics

A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer.

Power MOS transistor device

A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode. The vertical avalanche diode is configured to conduct breakdown current between the first and second faces in the off state of the device and having a first current carrying diode region of the second semiconductor type in contact with the first face and with the conductive layer and a second semiconductor region of the first semiconductor type electrically connected with the second face.

Power MOS transistor device and switch apparatus comprising the same

In one embodiment, an SCR device () includes a p+ wafer (), a p&#x2212; layer (), an n+ buried layer () and an n&#x2212; layer (). P&#x2212; wells () are formed in the n&#x2212; layer (). N+ regions () and p+ regions () are formed in the p&#x2212; wells (). A first ohmic contact () couples one n+ regions () to one p+ region (). A second ohmic contact () couples another n+ region () to another p+ region () to provide physically and electrically symmetrical low-voltage p-n-p-n silicon controlled rectifiers. A deep isolation trench () surrounding the SCR device () and dopant concentration profiles provide a low capacitance SCR design for protecting high frequency integrated circuits from electrostatic discharges.

Symmetrical high frequency SCR structure

A filter circuit () is formed on a semiconductor substrate () formed with a trench () that is lined with a dielectric layer (). A conductive material () is disposed in the trench and coupled to a node () to provide a capacitance that modifies a frequency response of an input signal (V) to produce a filtered signal (V). An electrostatic discharge device includes an inductor () coupled to back to back diodes () formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.

Growing community of inventors

Mauzac, France

Rene Escoffier