Commissariat a L'energie Atomique Et Aux Energies Alternatives

Centre National De La Recherche Scientifique

Alcatel Lucent

Renault S.a.s.

Rene Escoffier

Julien Buckley

Hubert Bono

Serge Loudot

Matthew Charles

Guy Feuillet

Jesus Zuniga Perez

Yannick Baines

Thierry Bouchet

Blandine Alloing

Roy Dagher

A method for obtaining mesas that are made at least in part of a nitride (N), the method includes providing a stack comprising a substrate and at least the following layers disposed in succession from the substrate a first layer, referred to as the flow layer, and a second, crystalline layer, referred to as the crystalline layer; forming pads by etching the crystalline layer and at least one portion of the flow layer such that: —each pad includes at least: —a first section, referred to as the flow section, formed by at least one portion of the flow layer, and a second, crystalline section, referred to as the crystalline section, framed by the crystalline layer and overlying the flow section, the pads are distributed over the substrate so as to form a plurality of sets of pads; and epitaxially growing a crystallite on at least some of said pads and continuing the epitaxial growth of the crystallites until the crystallites carried by the adjacent pads of the same set coalesce.

Method for producing nitride mesas each intended to form an electronic or optoelectronic device

The invention concerns a heterojunction field-effect transistor comprising a stack of first and second III-N type semiconducting layers forming an electron gas or hole layer; a first conduction electrode in electrical contact with the gas layer and a second conduction electrode; a separation layer positioned vertically in line with the first electrode and under the second semiconducting layer; a third semiconducting layer arranged under the separation layer and in electrical contact with the second electrode; a conductive element in electrical contact with the gas layer and electrically connecting the third semiconducting layer and the gas layer; and a control gate positioned between the conductive element and the first conduction electrode.

Heterojunction transistor with vertical structure

A normally-off heterojunction field-effect transistor is provided, including a superposition of a first layer, of III-N type, and of a second layer, of III-N type, so as to form a two-dimensional electron gas; a stack of an n-doped third layer making electrical contact with the second layer, and of a p-doped fourth layer placed in contact with and on the third layer, a first conductive electrode and a second conductive electrode making electrical contact with the two-dimensional electron gas; a dielectric layer disposed against a lateral face of the fourth layer; and a control electrode separated from the lateral face of the fourth layer by the dielectric layer.

Open type heterojunction transistor having a reduced transition resistance

An optocoupler is provided, including at least one light source and at least one matrix of photovoltaic cells facing the at least one light source, the at least one light source being configured to receive, at an input, an input electrical signal, and to generate, at an output, according to the input electrical signal, a light signal, sent to the at least one matrix of photovoltaic cells, the at least one matrix of photovoltaic cells being configured to receive, at the input, at least partially the light signal and to deliver, at the output, at least one output electrical signal, at the level of at least two connection pads, and the at least one light source being a matrix of laser diodes.

Optocoupler

A bidirectional heterojunction transistor includes first and second conduction electrodes, first and second gates between the conduction electrodes, and first and second reference electrodes between the gates. The transistor further includes a superposition of semiconductor layers, including channel zones that are vertically in line with the gates, a first conduction zone between the first conduction electrode and the first channel zone, and a second conduction zone between the second conduction electrode and the second channel zone. The superposition of semiconductor layers also includes a third conduction zone that is separated from the first and second conduction zones by the first and second channel zones, respectively, and a first electrical connection that is connected to the third conduction zone and to the first reference electrode.

Bidirectional transistor having a low resistance heterojunction in an on state

An electronic circuit is provided, including, on one same substrate, an inverter branch formed by high side and low side transistors, and the drivers of the high side and the low side transistors. The drivers include logic gates configured to receive one same PWM input signal and to generate two alternated command signals sent to the high side and the low side transistors. An inverter system is also provided, including the electronic circuit and laser optocouplers configured to electrically insulate the electronic circuit of a controller delivering a pulse width modulation (PWM) input signal and a main supply electrically supplying the drivers.

Inverter branch driver

A protection circuit including an input interface; an output interface; a current sensor connected between an input terminal and an output terminal; first and second HEMT transistors of normally closed type connected in series with the current sensor and connected in series by way of a connection node; a transformer, a primary winding of which is connected to the terminals of the current sensor; a rectifier bridge exhibiting two input terminals connected to the terminals of a secondary winding of the transformer, and exhibiting output terminals, an output terminal of the rectifier bridge being connected to the control gates of the transistors, an output terminal of the rectifier bridge being connected to the connection node.

Current limiter for AC load

An electronic device having at least a first HEMT transistor and bias circuit able to at least reverse bias the first HEMT transistor by applying an electric voltage Vof a positive value between a source of the first HEMT transistor and a drain of the first HEMT transistor. The first HEMT transistor is able to be ON when a value of an electric voltage Vbetween a gate of the first HEMT transistor and the drain of the first HEMT transistor is higher than a value of a threshold voltage Vof the first HEMT transistor. The electronic device has, during a forward biasing, a behavior similar to that of a forward biased or reverse biased Zener diode.

Electronic device with a reverse biased HEMT transistor

An apparatus includes a bidirectional hetero junction field-effect power transistor having a gate between conduction electrodes, semiconductor layers, one formed on the other, and the two meeting at an electron gas layer interface, and a reference electrode embedded in one layer. The reference electrode connects to a potential of a zone of the gas layer that is plumb with the reference electrode, A distance between the reference electrode and one conduction electrode and between the gate and that conduction electrode is between 45 and 55% of a distance between the conduction electrodes. A control circuit connected to the reference electrode generates a switching voltage for switching the transistor from a reference electrode voltage, and to apply a control voltage to the gate.

Growing community of inventors

La Buisse, France

Rene Escoffier