Marvellworld Trade Ltd.

Marvell International Limited

Tectus Corporation

Renaldi Winoto

David M Signoff

Li Lin

Jinho Park

Ming He

Wayne A Loeb

Paul Aerick Lambert

Michael West Wiemer

Ashkan Olyaei

Shu-Hsien Liao

Saeed Chehrazi

Ion E Opris

Paul Scott Martin

Joseph Czompo

David Cousinard

Ramin Mirjalili

Sai-Wang Tam

Abhishek Deepak Bhat

Dominic Philip Haine

Yuan Lu

Yi Zhao

Morteza Nick

Mohammad Hekmat

Shadi Youssef

Scott Herz

Philip Godoy

Li Hao

SeongHwan Cho

Mihai-Costin Manolescu

Xinhua Chen

A display device suitable for augmented reality glasses or other display applications includes a three panels of ultra-dense micro-LED arrays integrated in a compact form factor. The panels each monochromatically generate red, green, and blue components of an image, and an optical element optically combines the image components to form an output image. Each panel includes a backplane with timing logic and CMOS pixel drivers for driving the micro-LED arrays. The backplanes may be interconnected in a master-slave configuration in which a master backplane receives image data from a host processor and sends image data directly or indirectly to the slave backplanes. The master backplane may furthermore output various timing signals to the slave backplanes to synchronize output of the image components.

Backplane for multi-panel ultra-dense micro-LED display

A micro-LED display has an array of separately controllable micro-LEDs and corresponding pixel drivers. The pixel drivers have pulse-width modulation (PWM) generator circuits for the LEDs. The PWM generator circuits include the following. N input nodes are coupled to receive N control bits that determine a brightness of the LEDs. An output node is coupled to output the drive signal to the LEDs. Each of N transistors are connected between one of the input nodes and the output node. Each transistor is controlled by a clock signal CKand couples the input node to the output node as controlled by the clock signal CK.

Compact pixel driver for micro-LED displays

Described herein are systems and methods that allow for secure wireless communication between a contact lens system and an accessory device to protect sensitive data and prevent unauthorized access to confidential information. In certain embodiments, tampering attempts by potential attackers are thwarted by using a Physically Unclonable Functions (PUF) circuit that is immune to reverse engineering. In addition, sensors monitor a to-be-protected electronic device to detect tampering attempts and physical attacks to ensure the physical integrity of the communication system.

Secure communication between a contact lens and an accessory device

Presented are eye-controlled user-machine interaction systems and methods that, based on input variables that comprise orientation and motion of an electronic contact lens, assist the wearer of the contact lens carrying a femtoprojector to control and navigate a virtual scene that may be superimposed onto the real-world environment. Various embodiments provide for smooth, intuitive, and naturally flowing eye-controlled, interactive operations between the wearer and a virtual environment. In certain embodiments, eye motion information is used to wake a smart electronic contact lens, activate tools in a virtual scene, or any combination thereof without the need for blinking, winking, hand gestures, and use of buttons.

Eye-based activation and tool selection systems and methods

A device for communicating data with a contact lens through a communication interface is disclosed. In embodiments of the invention, an accessory device identifies one or more wireless channels to communicate with a contact lens. Scheduling of this wireless communication is performed such that a preferred channel is selected based on noise and/or interference. In certain embodiments, a centralized scheduler, such as a Wi-Fi access point, is used to reserve the preferred channel within the associated wireless network so that clients within the network don't use this channel.

Wireless communication between a contact lens and an accessory device

An eye-mounted display includes a femtoprojector, which includes a backplane and a frontplane. The backplane receives data (e.g., data packets) that specify the image to be projected by the eye-mounted display. It converts this data to drive signals (e.g., current) to drive the frontplane. The frontplane contains an array of light emitters (e.g., LEDs) that produce light according to the drive signals, thus generating the desired image. In one approach, the image is deconstructed and transmitted to the backplane as needed as microframes which are displayed asynchronously and only for regions where the image has changed, rather than continuously scanning full picture frames at the full frame rate. In another aspect, the femtoprojector has variable pitch between adjacent light emitters.

Backplane for eye-mounted display

Systems, devices, and techniques for performing peak detection are described. A described receiver includes a first amplifier to amplify an input signal to generate a first amplified signal; a mixer to downconvert the first amplified signal to generate a downconverted signal; a second amplifier to amplify the downconverted signal to generate a second amplified signal; a filter, being selectably engageable by the receiver, a peak detector configured to perform voltage measurements of the second amplified signal; and switch circuitry. The switch circuitry is configured to selectably disengage the filter during a first measurement phase during which a first voltage measurement performed by the peak detector is indicative of an output voltage swing of the first amplifier, and to selectably engage the filter during a second measurement phase during which a second voltage measurement performed by the peak detector is indicative of an output voltage swing of the second amplifier.

RF peak detection method using a sequential baseband scheme

A power amplifier includes an array of transistors having outputs that are connected in parallel to one another and coupled to an output network. The power amplifier further includes digital circuitry, configured to receive a sequence of control words that specify respective amplitudes of a signal to be transmitted in respective time intervals, and to transmit the signal by performing, for each control word and respective time interval: partitioning the control word into a Least Significant Bit (LSB) portion and a Most Significant Bit (MSB) portion; selecting a time duration based on the LSB portion; selecting an amplitude based on the MSB portion; and activating the array of transistors during the time interval in accordance with the selected time duration and the selected amplitude.

High-efficiency RF digital power amplifier with joint duty-cycle/amplitude modulation

Systems and techniques relating to wireless communication devices and reconfigurable an integrated RF Front-End for dual-band WLAN transceivers include, according to an aspect, an integrated circuit chip comprising: radio frequency (RF) Front-End circuitry, wherein the RF Front-End circuitry comprises (i) an antenna input line configured to connect with one or more antennas of a wireless communication device, (ii) a transmitter input line, (ii) a first receiver output line, (iii) and a second receiver output line; harmonic trap circuitry coupled with the RF Front-End circuitry via the antenna input line, the harmonic trap circuitry being fully integrated on the integrated circuit chip.

Reconfigurable integrated RF front-end for dual-band WLAN transceivers

An apparatus includes a first circuit transmitting a first signal to a port, a second circuit receiving a second signal from the port, a first peak-notch filter coupled between the port and the first circuit and configured to pass the first signal and block the second signal, a second peak-notch filter coupled between the port and the second circuit and configured to pass the second signal and block the first signal, and a third filter coupled between an input of the first filter and a ground or between an output of the second filter and the ground. The first signal has a first frequency and the second signal has a second frequency that is different from the first frequency.

Integrated duplexer

A circuit includes a reference voltage circuit, a filter circuit configured to receive an output of the reference voltage circuit, and a voltage follower configured to receive an output of the filter circuit and generate a bias voltage. The filter circuit is configured to combine signals on a reference ground with the output of the reference voltage circuit. A method of providing a bias voltage includes generating a reference voltage using a reference voltage circuit, filtering the reference voltage to generate a second voltage using a filter circuit, and generating the bias voltage according to the second voltage using a voltage follower circuit. Filtering the reference voltage includes combining a fluctuation of the reference ground with the reference voltage.

Memory effect reduction using low impedance cascode biasing

The present disclosure includes systems and techniques relating to calibrating I/Q mismatches in communication systems. In some implementations, a reference signal to be transmitted by a transmitter (Tx) is identified. A loopback signal corresponding to the reference signal is generated by passing the reference signal through the TX and a receiver (Rx). The loopback signal includes an additional signal that distinguishes an in-phase/quadrature (I/Q) mismatch caused by the Tx (Tx I/Q mismatch) from an I/Q mismatch caused by the Rx (RX I/Q mismatch). A set of Tx I/Q mismatch parameters and a set of Rx I/Q mismatch parameters are determined based on the reference signal and the loopback signal, using the additional signal. A Tx signal is calibrated based on the set of Tx I/Q mismatch parameters, while a Rx signal is calibrated based on the set of Rx I/Q mismatch parameters, independently from the calibrating the Tx signal.

Adaptive I/O mismatch calibration

An apparatus comprises an amplifier and a pre-distortion circuit coupled to an input of the amplifier. A saturation value of an input signal corresponds to a maximum output power of an output signal of the amplifier. An input target value of the input signal is determined according to the saturation value. The input target value is determined by subtracting an offset from the saturation value or by multiplying a ratio by the saturation value. An average value or an RMS value of the input signal is controlled to be substantially equal to the input target value. A method comprises determining an input target value according to a saturation value, and controlling an input signal according to the input target value.

Pre-distortion based power control

Systems and techniques relating to wireless communication devices and digital power amplifiers include, according to an aspect, an apparatus including: processor electronics; transceiver electronics coupled with the processor electronics, the transceiver electronics including modulation circuitry and a digital power amplifier coupled with the modulation circuitry; a clock source coupled with the transceiver electronics to provide a clock signal from the clock source to the digital power amplifier at a sampling clock frequency; a local oscillator coupled with the transceiver electronics to provide a local oscillator signal from the local oscillator to the modulation circuitry at a local oscillator frequency; and one or more antennas coupled with the digital power amplifier in the transceiver electronics; wherein the local oscillator frequency is an integer multiple of the sampling clock frequency; and wherein a parasitic frequency response of circuitry in the transceiver electronics acts as an implicit out-of-band filter to remove alias signals.

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Danville, CA, United States of America

Renaldi Winoto