Jmicron Technology Corp.

Ren-Yuan Huang

Yi-Ren Hwang

An impedance matching circuit includes a plurality of latch circuits, each connected to one of a plurality of logic circuits. Each latch circuit has a first input commonly connected to a signal line and a second input connected to one of a plurality of non-overlapping digital clock signals. Approximately half of the maximum output resistance is compared with an external resistor and the result latched by a latch circuit corresponding to the most significant bit of the control signal, effectively halving the possible voltage range. A next latch circuit latches the second most significant bit of the control signal similarly, and a third latch circuit latches the remaining bit of the control signal. The control signal controls a binary weighted transistor array that adjusts input voltage. An output signal goes to an output register where it is used to control an output driver.

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Irvine, CA, United States of America

Ren-Yuan Huang