Tsinghua University

Synopsys, Inc.

Springsoft, Inc.

Synopsys Taiwan Co., Ltd.

Springsoft Usa, Inc.

Ren-Song Tsay

Wai-Kei Mak

Sheng-Hsiung Chen

Fong-Yuan Chang

Tung-Chieh Chen

Meng-Huan Wu

Fong-yuan Chang

Cheng-Yang Fu

Peng-Chih Wang

Tzu-Chi Huang

A computer implemented method for routing a first path in a circuit design is presented. The method includes iteratively building a multitude of partial-paths to route the first path by adding an incremental length to a selected previously built partial-path when the computer is invoked to route the first path in the circuit design, the adding being performed in accordance with at least a first design rule. The multitude of partial-paths start at a first location. The method further includes comparing each of the multitude of partial-paths to each other when the multitude of partial-paths end on a common second location different from the first location, and saving one of the multitude of partial-paths that leads to a shortest first path. The method further includes eliminating one of the multitude of partial-paths that are not selected to lead to the shortest first path.

Separation and minimum wire length constrained maze routing method and system

A computer implemented method for designing an integrated circuit (IC) having dimensions along first and second directions, and comprising at least a first block is presented. The method includes evaluating a demand ratio for the first block, the demand ratio being reflective of a ratio of a conductive wiring demand along the first direction and a conductive wiring demand along the second direction, when the computer is invoked to evaluate the demand ratio for the first block. The method further includes creating one or more wiring reservation blocks in accordance with the demand ratio.

Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratios

The present invention provides a method for efficient resource-oriented power evaluation. By mapping instructions to microarchitecture components, both advantages of high-level simulation performance and fine-grained power model are obtained. The present invention effectively reduces simulation runtime overhead and provides an accurate power estimation result. The present invention is nearly as accurate as gate-level simulators, with an error rate of less than 1.2 while achieving simulation speeds of up to 20 MIPS, five orders faster than a commercial gate-level simulator. By using the present invention, it is easy to analyze power consumption profile and peak power.

Resource-oriented method of power analysis for embedded system

A method for designing and making an integrated circuit is described. That method utilizes statistical models of wire segments to accurately estimate the expected length of minimum-length, orthogonal wire segments within a block. From these estimates, the method accurately estimates an ratio between the horizontal and vertical routing resources required, termed the 'H/V Demand Ratio.' From the H/V Demand Ratio, an accurate estimate of the height and width of the block may be determined. Thereafter, placement and routing may be performed quickly and accurately, thereby allowing the block to be designed and manufactured quickly and cost effectively. A method for designing an integrated circuit with efficient metal-1 resource utilization is also described.

Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio

The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.

Method, system and computer readable storage device for generating software transaction-level modeling (TLM) model

The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization.

High-parallelism synchronization approach for multi-core instruction-set simulation

The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.

Method and device for multi-core instruction-set simulation

A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero.

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Chu-Pei, Taiwan

Ren-Song Tsay