Raydium Semiconductor Corporation

Raydlum Semiconductor Corporation

Ren-Feng Huang

Ko-Yang Tso

Chin-Chieh Chao

Hui Wen Miao

Hui-Wen Miao

Yann-Hsiung Liang

A sampling phase selection method for a data stream is provided, wherein the data stream has a variable data rate in a fixed time period. The method comprises generating a calibration signal, wherein the time interval of the calibration signal is longer than the fixed time period of the data stream, generating a first clock sequence and a subsequent second clock sequence, wherein the first and the second clock sequence are composed of a plurality of continuous clock phases and the number of the clock phases of the first clock sequence are the same as that of the clock phases of the second clock sequence, selecting one of the phases of the first and the second clock sequence, in turn, to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, and selecting a final sampling phase according to the flag signals with different sampling phases.

Sampling phase selection method for a stream of data bits

The current disclosure discloses a sampling phase selection method for a data stream, wherein the data stream has a variable data rate in a fixed time period. The method comprises the following steps: generating M section signals with the same time interval during the fixed time period of the data stream, generating N continuous clock phases according to a rising edge of each of the section signals, selecting one of the continuous clock phases corresponding to the different section signals in turn to provide a sampling phase, performing a plurality of samplings on the data stream to generate a flag signal, repeating the selecting and the sampling steps to generate N flag signals corresponding to the different section signals, and selecting a final sampling phase according to the N flag signals corresponding to the different section signals.

A signal circuit includes a clock terminal for transmitting a reference clock and a data terminal for transmitting an input/output data. In an embodiment, the frequency of the reference clock is one-eighth of the bit rate of the input/output data.

Signal circuit

A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.

Sampling clock selection module of serial data stream

A source driver and a receiver thereof are disclosed. A two-stage amplifier of the receiver includes a first-stage circuit and a second-stage circuit. The second-stage circuit includes a first switch, a second switch, a third switch, a first node, and a second node. The first switch is coupled between the first node and a ground end; the second switch is coupled between the second node and the ground end; the third switch is coupled between the first node and the second node. When the receiver wants to wake up from a power-saving mode to a normal operation mode, the first switch and the second switch are switched to the off-state according to a control signal at first; after a period of delay time, the third switch is also switched to the off-state according to a delayed control signal.

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Kaohsiung, Taiwan

Ren-Feng Huang