Realtek Semiconductor Inc.

Ren-Chieh Liu

Chao-Cheng Lee

Han-Chang Kang

Turut Sefket Aytur

A mixer device includes a differential circuit, a transconductance circuit, and a selecting circuit. The differential circuit receives a differential input signal and generates a differential output signal. The transconductance circuit is coupled to the differential circuit, receives a plurality of radio frequency input signals, and determines to mix at least one of the radio frequency input signals with the differential input signal according to an enable signal. The selecting circuit receives a control signal and generates the enable signal according to the control signal.

Multi-input mixer, mixer device, and mixing method

A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches.

Switch circuit having adjustable linearity of differential mode resistances

A DC offset calibration apparatus includes a first adjustment unit, a first offset calibration circuit, a second adjustment unit, and a second offset calibration circuit. The first adjustment unit adjusts a first input signal to generate a first output signal according to a first offset calibration signal. The first offset calibration circuit is coupled to the first output signal and the first adjustment unit for determining the first offset calibration signal according to the first output signal and predetermined threshold value. The second adjustment unit adjusts a second input signal to generate a second output signal according to a second offset calibration signal. The second offset calibration circuit is coupled to the second output signal and the second adjustment unit for determining the second offset calibration signal according to the second output signal and the predetermined threshold value. The first and the second input signals are a differential signal pair.

DC offset calibration apparatus and method for differential signals

Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.

Multi-loop phase locked loop circuit

The present invention discloses an adjustable gain power amplifier circuit. The adjustable gain power amplifier circuit includes a power amplifying unit for receiving and amplifying an input signal to generate an output signal; a power detecting unit for detecting power of the input signal to generate a detecting signal; and a biasing control unit for generating a biasing signal according to the detecting signal and to output the biasing signal.

Power amplifier circuit having a bias signal inputted into input terminal and method thereof

A DC offset calibration apparatus is disclosed. The DC offset calibration apparatus includes an adjustment circuit and an offset calibration circuit. The adjustment circuit is utilized for receiving an input signal and an offset calibration signal, and for adjusting the input signal to generate an output signal according to the offset calibration signal. The offset calibration circuit is coupled to the output signal and to the adjustment circuit for determining the offset calibration signal according to at least the output signal and a predetermined threshold value.

DC offset calibration apparatus and method

The present invention discloses a frequency synthesizer, including: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, for selecting a specific clock signal from the clock signals as an output clock signal, wherein a specific frequency locking circuit of the frequency locking circuits locks the specific clock signal; and a control circuit, for controlling the frequency locking circuits. The control circuit controls at least one of the frequency locking circuits apart from the specific frequency locking circuit to lock another clock signal according to another reference clock signal at the same time. A related method for frequency synthesizing is also disclosed.

Frequency synthesizer with a plurality of frequency locking circuits

A charge pump circuit capable of canceling current mismatch and suppressing clock feedthrough. The charge pump circuit comprises a current source enabled by a first logical signal, a current sink enabled by a second logical signal, an integrating capacitor coupled to both the current source and the current sink, and a switching device coupled between the integrating circuit and an output node. The switching device has two states. The switching device is set to a first state whenever a third logical signal is asserted and one of the first logical signal, the second logical signal, and a modulating signal is enabled. The switching device is set to a second state whenever the third logical signal is de-asserted, or none of the first logical signal, the second logical signal, and the modulating signal are asserted.

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Chang-Hua Hsien, Taiwan

Ren-Chieh Liu