Lsi Logic Corporation

Marseille Networks, Inc.

Remi C Lenoir

Lawrence S Yeung

Ho-Ming Leung

Eric Hung

Vijendra Kuroodi

Geeta K Desai

Timothy J Wilson

Zoltan Toth

Daniel S Perrin

A system transmits video content from a single video source or multiple independent video sources by transmitting at least one data information segment (DIS) followed by a plurality of video data information segments (VDIS). Each DIS includes information that corresponds to a video source and to the plurality of VDIS transmitted subsequently. A receiver system receives at least one DIS followed by a plurality of VDIS, and processes the received VDIS in accordance with the information in the received DIS. The receiver system stores processed video content of the processed VDIS into a memory queue, and a separate memory queue is used for each video source. A display interface receives and processes video content of each memory queue to generate video pixels of a respective output image in accordance with preselected preferences, e.g., corresponding video source, video format, resolution, and/or starting location of the respective output image.

Segmented video data processing

A system comprising a single or multiple independent video sources, where each video source manages to transmit its video data information using a predefined video segment size. The system comprises a segmented video data processing unit that receives the transmitted video segments, groups and processes the received video segments in accordance with the corresponding video source, produce video data information from the received video segments, and stores in proper order the processed video data information from a single source into a single memory queue. An output display processing unit receives the video data information from at least one of the memory queues, and manages the processing and formatting of the received video data information in accordance with preselected preferences such as output image video format, resolution, and/or starting location of a first video pixel of the output image. The processed and formatted video data information is used to display the output image using a high resolution electronic display.

System for segmented video data processing

An apparatus comprising a first portion, a second portion and a processor. The first portion is configured to generate a count signal in response to a number of oscillations of a clock signal. The first portion is powered by an unswitched power source. The second portion is configured to generate an interrupt signal in response to the count signal and a predetermined stored value. The second portion is powered by a switched power source. The processor is configured to (i) receive the interrupt signal and (ii) generate the switched power.

Real time clock architecture and/or method for a system on a chip (SOC) application

A semiconductor memory device is provided as well as a method for operating the semiconductor memory device. The memory device includes a NOR array of memory cells and a NAND array of memory cells configured on the same monolithic semiconductor substrate. Each cell of the NOR array involves a single transistor, similar to each cell of the NAND array. The memory device is, therefore, an integrated circuit that includes not only the NOR and NAND arrays, but also the row and column decoders corresponding to each array. Furthermore, the integrated circuit includes the interface circuitry needed to transfer information as pages into and from the NAND array. The corresponding interface or controller is implemented on the same monolithic substrate as both the NAND array and the NOR array. Addresses targeted for the NOR array are sent as fully memory-mapped data into the NOR array, whereas addresses targeted for the NAND array are sent through the controller integrated within the semiconductor memory device. The single transistor cell of both the NAND array and NOR array preferably involves a flash EEPROM-type transistor that implements a floating gate dielectrically spaced between a control gate and the semiconductor substrate.

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Menlo Park, CA, United States of America

Remi C Lenoir