Nxp B.v.

St-ericsson Sa

Remco Van De Beek

Massimo Ciacci

Jos Verlinden

Ghiath Al-kadi

Charles John Razzell

Stefan Mendel

Ghiath Al-Kadi

Domine Leenaerts

Jozef R M Ervoet

Jozef R M Bergervoet

A load-modulation detection component for an inductive coupling reader device. The load-modulation receiver device is arranged to receive an antenna voltage signal representative of a voltage across an antenna of the inductive coupling reader device and output at least one load-modulated signal. The load-modulation detection component comprises a down-converter component arranged to mix the antenna voltage signal with a down-conversion signal to generate a down-converted signal, a series capacitive component coupled in series between an output of the down-converter component and an output of the load-modulation receiver, and a switched capacitor resistor circuit coupled between the output of the load-modulation receiver and a first reference voltage.

Load-modulation detection component

Apparatus for clock synchronization comprising a first phase locked loop () and a second phase locked loop (). The first phase locked loop () is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop () comprises a frequency divider () that controls the multiple in response to a control signal. The second phase locked loop () is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (). The second phase locked loop () comprises phase adjustment means (), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

Clock synchronizer

A digital synchronizer is disclosed with a phase locked loop and a carrier generator. The phase locked loop is configured to produce an output signal having the same frequency as an input signal by selecting a divider ratio of a frequency divider with a control signal, the frequency divider divides the frequency of a high frequency signal by the divider ratio to provide the output signal; carrier generator is configured to generate an oversampled carrier signal by using the control signal to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal.

Digital synchronizer

Embodiments of power source circuits and methods for operating a power source circuit are described. In one embodiment, a method for operating a power source circuit involves receiving at the power source circuit at least one digital signal from a feedback loop and increasing or decreasing an output power signal of the power source circuit in response to the at least one digital signal. Other embodiments are also described.

Digitally controllable power source

A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analog-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.

Wireless receiver and method

An apparatus for detecting the end of a communication is disclosed. The apparatus includes an interface circuit for receiving an encoded signal and a carrier signal recovery circuit coupled to an output of the interface circuit. The carrier signal recovery circuit is configured to output a carrier signal of the encoded signal and a second signal that is out of phase with the carrier signal. The apparatus also includes a decoding circuit configured to decode the encoded signal as a function of both the encoded signal and the carrier signal output by the carrier signal recovery circuit. The apparatus also includes a detection circuit configured to detect an indication of an end of a communication in the encoded signal as a function of both the encoded signal and the second signal.

End of communication detection

A symbol clock recovery circuit comprising an ADC, a controllable inverter and a timing detector. A timing detector input terminal is configured to receive an ADC output signal from an ADC output terminal; a timing detector output terminal is configured to provide a digital output signal; and a first timing detector feedback terminal is configured to provide a first feedback signal to the inverter control terminal. The timing detector is configured to determine an error signal associated with the received ADC output signal, and set the first feedback signal in accordance with the error signal.

Symbol clock recovery circuit

Configurable suppression of harmonics in a radio frequency (RF) transmitter circuit having two class-D switching amplifiers that produce a differential output signal having introduced harmonics is contemplated. A selected harmonic is used to determine a time duration. A harmonic suppression circuit modifies a radio frequency polar modulated data signal that is encoded using an amplitude component and a phase component. The modification is responsive to the determined time duration. The switching power amplifiers amplify the modified polar modulated data signal to produce an amplified signal. The amplified signal includes three signal levels, a high signal level, a middle signal level and a low signal level. The timing of transitions between the high and low signal levels represents the phase component, and the transitions include the middle signal level for the time duration, thereby suppressing the selected harmonic.

Harmonic suppression in switching amplifiers

Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.

Amplifier with filtering

In one or more embodiments, a system is provided for communicating between different voltage domains using N+1 capacitive-coupled conductive lines to provide N communication channels. For instance, bi-directional communication (e.g., a first communication in a first direction and a second communication path in the opposite direction) may be provided using three capacitive-coupled signal paths. Two of the signal paths are used as single-ended (i.e., non-differential) signal paths. The third signal path is used to suppress voltage disturbances between two voltage domains.

Communication interface for galvanic isolation

A signal processing circuit comprises a frequency up-conversion circuit () for performing up-conversion with a first local oscillator frequency and a frequency down-conversion circuit () for performing down-conversion with a second local oscillator frequency. A digital signal processor () controls supply first signals representing a first complex signal to the up-conversion circuit, and receives second signals representing a second complex signal. The digital signal processor controls a compensation of I/Q mismatch of results of up-conversion and/or down-conversion. The digital signal processor () switches to a calibration mode for selecting a parameter of said compensation. In the calibration mode the first and second local oscillator frequencies have a frequency offset with respect to each other. The digital signal processor () measures an amplitude of a frequency component at a frequency corresponding to mismatch in one and not more than one of the results of up-conversion and/or down-conversion, and selects the parameter dependent on the amplitude.

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Eindhoven, Netherlands

Remco Van De Beek