Nxp B.v.

Koninklijke Philips Corporation N.v.

Remco Cornelis Herman Van De Beek

Massimo Ciacci

Jos Verlinden

Ghiath Al-kadi

Jozef Reinerus Maria Bergervoet

Ghiath Al-Kadi

Cicero Silveira Vaucher

Bram Nauta

Dominicus Martinus Wilhelmus Leenaerts

Harish Kundur Subramaniyan

Eric Antonius Maria Klumperink

Sander Derksen

Liang Zhang

Juhui Li

Gerard Van Der Weide

Dobson Paul Parlindungan Simanjuntak

LiSong Feng

Alan Chang

Ghaith Al-kadi

An oscillator system includes a voltage controlled oscillator (VCO) circuit. The VCO circuit includes an output for providing an oscillation signal and input to receive a voltage that controls the frequency of the oscillation signal. The oscillator system includes a frequency to voltage circuit that receives the oscillation signal and produces a voltage that is dependent upon the frequency of the oscillation signal. The oscillator system includes a comparison circuit including an amplifier. The amplifier includes an inverting input, a non inverting input, and an output. During a first phase of the comparison circuit, the non inverting input receives a reference voltage and the inverting input is coupled to the output of the amplifier via a switch and to a capacitor wherein the capacitor samples the voltage of the output. During a second phase of the comparison circuit, the non inverting input receives the voltage produced by the frequency to voltage circuit and the switch between amplifier output and inverting input is open wherein the inverting input is coupled to the capacitor to receive the sampled voltage value. During the second phase, the output of the amplifier is provided to the input of the VCO circuit.

Oscillator system

The present disclosure relates in general to devices, systems and methods for wireless communication, and in particular to communication using a proximity integrated circuit card (PICC). Example embodiments include a circuit () for a PICC, the circuit comprising an input stage (), a decoding module () and a bias adjustment module (), the bias adjustment module () configured to receive an output code from the decoding module and provide a bias adjustment signal to the input stage (), the bias adjustment module () configured to iteratively tune the bias adjustment signal based on a measurement of the output code, with successive steps tuning the bias adjustment signal by a smaller amount until the output code is within a decoding range.

Adaptive bias tuning

An apparatus includes an antenna that is configured to transmit a radio frequency signal across a transmission media having a channel response impairment. A transmission path includes an encoder circuit that encodes data on a carrier signal; and a pre-equalizer circuit that is configured to pre-distort the encoded data according to equalizer coefficients representing the channel response impairment. A first equalization path includes circuitry that generates the equalizer coefficients based upon transients resulting from a presence change event for the carrier signal. A second equalization path includes circuitry that generates the equalizer coefficients based upon knowledge of encoded data on the carrier signal. Selection circuitry selects between the first equalization path and the second equalization path.

Equalization from presence change transients

A proximity integrated circuit card bias adjustment. In one example, a decoding circuit, having an decoding range, for translating a data-frame signal having an information portion and a bias portion into an output code; and a bias adjust circuit coupled to receive the output code from the decoding circuit, and adjust the bias portion of the data-frame signal such that the output code is within the decoding range is disclosed. In another example, a method for proximity integrated circuit card bias adjustment, comprising: translating a data-frame signal having an information portion and a bias portion into an output code; and adjusting the bias portion of the data-frame signal such that the output code is within a decoding range is disclosed.

Proximity integrated circuit card bias adjustment

The invention proposes a smart card which comprises a digital signal processing receiver that can automatically identify the type of a smart card reader based on the error vector magnitude of signals received from the reader. The digital signal processing receiver is able to reconfigure itself at runtime in order to optimally minimize its power consumption in dependence on the type of reader it is communicating with. Furthermore, the invention proposes a new preamble structure that comprises a basic part and an optional additional part.

Smart card

Equalization circuits and methods are implemented for a variety of applications. According to one such application, a transmitting device wirelessly communicates using an antenna. The device has a transmission circuit that is configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna and a remote device, the coupling occurring over a wireless medium. A receiver circuit of the transmitting device is configured and arranged to receive a second wireless signal that is from the antenna and that represents the first wireless signal as modified by the coupling occurring over the wireless medium. An error circuit of the device is configured and arranged to generate an error signal by comparing the first wireless signal to the second wireless signal. An equalizer circuit of the device is configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol interference by compensating for the error signal.

Adaptive equalizer and/or antenna tuning

Smart card with reconfigurable receiver

Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.

Clock synchronizer for aligning remote devices

Embodiments of a method for processing a baseband signal in a Direct Current (DC)-suppressed system, a system for processing a baseband signal in a DC-suppressed system, and a smart card are described. In one embodiment, a method for processing a baseband signal in a DC-suppressed system involves processing the baseband signal in the analog domain with a first high pass filter (HPF), converting the processed baseband signal to a digital signal, and processing the digital signal in the digital domain with a second HPF to provide a discrete-time differentiation of the baseband signal. Other embodiments are also described.

Receiver filter for DC-wander removal in a contactless smartcard

The method comprises receiving an input stream of symbols (x(i)) representing a phase change and magnitude of an RF signal, the magnitudes of the symbols are constant, the phase changes of the symbols encode digital information, and adjust the input stream of symbols to reduce inter-symbol interference. The adjusting iteratively determines a next symbol of the equalized stream (x'(n)) after receiving a next symbol of the input stream (x(n)) by multiplying the next symbol of the input stream (x(n)) with a next adjusting real number (a(n)), multiplying a previous symbol of the input stream (x(n&#x2212;1)) with a previous adjusting real number (a(n&#x2212;1)), the previous symbol being received before the next symbol of the input stream, and the next symbol of the equalized stream is computed from the multiplied next symbol and the multiplied previous symbol of the input stream.

Pre-equalizer for a digitally modulated RF signal and method

A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.

Symbol clock recovery circuit

A frequency hopping receiver circuit has a frequency converter () and a hopping control circuit () coupled to the frequency converter (), and configured to control frequency hopping of the received frequency, by controlling changes in frequency shift applied by the frequency converter (). The frequency change is applied in combination with a temporary reduction in conversion gain of the frequency converter () during the change in frequency shift. The frequency converter may contain a mixer (), a local oscillator circuit () and a controllable amplifier () coupled between the input of the frequency converter () and the mixer () or between the mixer () and the output of the frequency converter (), or between the local oscillator circuit () and the local oscillator input of the mixer (). In this case the hopping control circuit () has outputs coupled to a gain control input of the controllable amplifier () and a frequency control input of the local oscillator circuit (), to control the reduction in conversion gain and the change in frequency shift respectively.

Frequency hopping receiver circuit

The present invention relates to a gigitaol phaselocked loop DPLL () having a phase-to-digital P2D () with an enhanced bang-bang phase detector BBPD. Such a P2D () comprises a BBPD (), an additional digital circuit () including a sign detector (), a counter () and a mapping function (), and a summer block (). During the locking process, the BBPD () may-output a repeating value, namely a string of data bits of same polarity value either '+1' or '&#x2212;1'. The polarity sign is detected by the sign detector (), and the data string length is determined by the counter () that is reset to zero whenever the BBPD output changes sign. The mapping function () is configured for mapping the data string length in input to the phase correction level in output Its output is added to that of the BBPD () through the summer block (), such that the phase correction level is increased to enhance the locking process whenever a data string is detected.

Fast-locking bang-bang PLL with low ouput jitter

An oscillation signal with a selectable frequency is generated with a phase locked loop (). The oscillator () of the loop receives a feedback signal, to which an offset is added in order to reduce transient effects when a frequency modification is made. A first and second offset control value are used to control the offset successively. The first offset control value is controlled by a combination of the frequency settings before and after the modification. The second offset control value is controlled by the frequency settings after the modification. The first and second offset control values are used to control an offset of applying to a frequency control signal of an oscillator () of the phase locked loop (). The offset controlled by the first control offset value is applied during a predetermined time interval before the offset controlled by the second control offset value is applied.

Electronic circuit frequency generation

The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means () of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers () added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

Growing community of inventors

Eindhoven, Netherlands

Remco Cornelis Herman Van De Beek