Intel Corporation

Rekha Manjunath

Srajudheen Makkadayil

Gabriele Boschi

Alessandro Campinoti

Tarjinder Singh

Vikram Sharma Mailthody

Saurabh Patil

Bakshree Mishra

A fault detector has a processor configured to receive, during a register write event, first data that are to be stored on a first register; determine a first encoded value from the first data using an encoding operation; receive second data from the first register from one or more bit locations on which the first data were to be stored; determine a second encoded value from the second data using the encoding operation; and compare the first encoded value and the second encoded value. If the first encoded value is the same as the second encoded value, the fault detector operates according to a first operational mode; and if the first encoded value is different from the second encoded value, the fault detector operates according to a second operational mode.

Register fault detector

An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.

Systolic array of pipelined processing engines for implementing dynamic programming algorithms

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Bengaluru, India

Rekha Manjunath