Qualcomm Incorporated

Rejeesh Ammanath Vijayan

Rahul Sahu

Pradeep Raj

A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

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Bengaluru, India

Rejeesh Ammanath Vijayan