Siemens Aktiengesellschaft

Reinhard Tielert

Lothar Risch

Andreas Hildebrandt

Wolfgang Peter Mueller

Ingmar Feigt

Christoph Werner

Bernd Zehner

The circuit arrangement and method is for measuring a difference in capacitance between a first capacitance (C.sub.1) and a second capacitance (C.sub.2). A hitherto necessary compensation of a plurality of parasitic effects has become unnecessary due to isolated measurement of an unwanted capacitance (C.sub.P) with which parasitic effects, to which the first capacitance (C.sub.1) and the second capacitance (C.sub.2) are subject, are modelled. When an evaluation logic (AL) realized in digital form is employed, only one counter unit wherein a binary value proportional to the respectively measured capacitance is counted need be provided. By cyclical measurement of the unwanted capacitance (C.sub.P), the first capacitance (C.sub.1), the second capacitance (C.sub.2) and, at the end, the unwanted capacitance (C.sub.P) are determined. The unwanted capacitance (C.sub.P) is compensated when the counter unit respectively counts backward when 'counting' the unwanted capacitance (C.sub.P) but otherwise counts forward. Each sub-cycle (T1,T2,T3,T4) lasts exactly N clocks, whereby the clocks are supplied by a measuring oscillator (MO). The clocks are dependent on the capacitance respectively measured.

Circuit arrangement and method for measuring a difference in capacitance

In a circuit arrangement for determining differences in capacitance, two capacitors (1,2) are alternately connected to an integrator with differential amplifier (3) whose input current is positive (+I) when the first capacitor (1) is integrated or negative (-I) when the second capacitor (2) is integrated, whereby the switches (5,6,7) are synchronously switched. The differential amplifier keeps the voltages at the two capacitors the same. A clocked control device (4) controls the synchronous switching and separately measures and adds the respective charging and discharging times and, as warranted, measures and adds the output voltage of the integrator and controls the last charging cycle such that the voltage at the capacitors is subsequently equal to the initial voltage. The relative or absolute differences in capacitance are calculated from the identified sums and can be digitally output.

Circuit arrangement for determining differences in capacitance

A voltage-stable sub-.mu.m-MOS transistor for VLSI circuits consist of a low-resistant silicon substrate of a first conductivity type with a high-resistant, thin, epitaxial layer of the first conductivity type situated thereon and on which a gate electrode consisting of polysilicon is disposed. Highly doped source/drain zones of the second conductivity type form a channel region of the first conductivity type. A doping substance concentration, rising in the direction of the substrate, is generated by means of double implantation, whereby the concentration maximum extends to behind the source/drain zones. A method for manufacturing same incorporates steps of forming the several layers, applying a mask, executing a double implantation in the channel region, and forming the gate electrode.

Voltage-stable sub-.mu.m MOS transistor for VLSI circuits

A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.

Large scale integrable memory cell with a trench capacitor wherein the

A circuit arrangement comprises a matrix-shaped memory arrangement for digital filtration of image signals in row and column directions and contains three-transistor cells having overlapping write/read cycles as storage elements. A row selector is clocked controlled by the input clock of the incoming image signals and is continuously steppable and resettable at any time. The row selector comprises, respectively, two phase offset signal outputs per selection step which respectively drive a write word line and a read word line and which are provided per row of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of the column. A storage amplifier which is disconnectible from the read bit line is provided per column and has an input connected to the read bit line of the assigned column and an output connected to the bit write line of the following column and serves as a data output. A reset input is connected to the setting inputs of a first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time to be set between the undelayed data output and a first, delayed data output. A plurality of such memory-shaped memory arrangements is provided in accordance with the word width of the image data the row selector being provided in common for such plurality, whereby a respective memory block accepts one bit of the image data word and offers the same as the respective corresponding bit of a plurality of differently time delayed output data words. An arithmetic unit combines the data outputs, by adding or, respectively, subtracting, in an arrangement of cascaded logic elements in order to achieve the required filter function.

Circuit arrangement comprising a matrix-shaped memory arrangement for

A circuit arrangement for providing a variably adjustable time delay of digital signals comprises a matrix-shaped memory arrangement having storage elements with overlapping write/read cycles. A clock-controlled, continuously steppable row selector normally cyclically circulates, but can be reset at any time. The row selector comprises two mutually phase offset signal outputs per selection step which respectively drive a write word line and a read word line of a word of the matrix. Two separate bit lines, a write bit line and a read bit line, are provided per column and are respectively interconnected to all memory cells of a column. The data input for the data signal to be delayed is connectible to all write bit lines via gates individually assigned to the columns, whereby only one of m gates is activated at a time by the column selector.

A circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable time delay of digital signals contains known three-transistor cells having overlap write/read cycles as storing elements. The arrangement also contains a continuously steppable row selector, resettable at any time, and clock-controlled by the input data clock which comprises, respectively, two mutually phase offset signal outputs per selection step which respectively drive a write word line and a read word line which are provided per row of the matrix. The arrangement further comprises two separate bit lines, a write bit line and a read bit line per column which are respectively interconnected to all memory cells of a column, and comprises a disconnectible storage amplifier per column whose input is connected to the read bit line of the column assigned thereto and whose output is connected to the following column and serves as a data output for the assigned column. The arrangement further comprises a data input for the data signals to be delayed, the data input being connected to the write bit line of the first column and to an undelayed data output, and a reset input which is connected to the setting inputs of a first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time which is to be set between the undelayed data output and the first delayed data output.

Circuit arrangement comprising a matrix shaped memory arrangement for

In an exemplary embodiment, an electrical charge image is scanned by a matrix of integrated MOS components with a floating gate (or a switched floating gate), functioning as a matrix of potential sensors, to produce an image signal for display on a video screen. A minimum field effect transistor with source-follower circuitry is preferably employed as the potential sensor; the sensor outputs are linked to a shift register. The new component is suitable for employment for potential measurements in X-ray diagnostics.

Arrangement for contact-free measurement of electrical charge images in

A process is disclosed for the production of a MIS field effect transistor having an adjustable, extremely short channel length. The effective channel length is set by superimposing at least two implantation steps employing differing implantation energy and doses. A gate electrode which possesses vertically etched edges is used as an implantation mask for the source implantation and drain implantation. The process allows a MOS structure having an arbitrarily small effective channel length to be constructed by exploiting the lateral scattering which occurs during the ion implantation without influence by mask tolerances. The process corresponding to the theory of the invention provides the possibility of constructing a DIMOS-similar transistor having typical structural dimensions in the region of 1 .mu.m and less.

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Munich, Germany

Reinhard Tielert