Siltronic Ag

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Wacker-chemitronic Gesellschaft Fur Elektronik-grundstoffe Mbh

Wacker Siltronic Gesellschaft F&uuml;r Halbleiter Materialien Ag

Silitronic Ag

Reinhard Schauer

Norbert Werner

Christian Hager

Joerg Haberecht

Peter Storck

Friedrich Passek

Wolfgang Siebert

Klaus Messmann

R&uuml;diger Schmolke

Dieter Gr&auml;f

Patrick Moos

Frank Laube

Rene Stein

Stephan Heinrich

G&uuml;nther Obermeier

Martin Pickel

Thorsten Schneppensieper

Variations in wafer thickness due to non-uniform CVD depositions at angular positions corresponding to crystallographic orientation of the wafer are reduced by providing a ring below the susceptor having inward projections at azimuthal positions which reduce radiant heat impinging upon the wafer at positions of increased deposition.

Method for depositing an epitaxial layer on a front side of a semiconductor wafer, and device for carrying out the method

A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.

Epitaxially coated semiconductor wafer of monocrystalline silicon and method for production thereof

A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.

Susceptor for holding a semiconductor wafer having an orientation notch, a method for depositing a layer on a semiconductor wafer, and semiconductor wafer

A susceptor for holding a semiconductor wafer with an orientation notch during deposition of a layer on the wafer comprises a susceptor ring having a placement area for placing the semiconductor wafer in the edge region of a back side of the semiconductor wafer and a step-shaped outer delimitation of the susceptor ring adjoining the placement area. The susceptor has four positions at which the structure differs from the structure at four further positions, the spacing from one of the four positions to the next of the four positions being 90&#xb0;, the spacing from one of the four positions to the next further position being 45&#xb0;, one of the four positions being a notch position at which the structure of the susceptor differs from the structure of the susceptor at the three other positions of the four positions of the susceptor.

Susceptor for holding a semiconductor wafer with an orientation notch during the deposition of a layer on a front side of the semiconductor wafer and method for depositing the layer by using the susceptor

Semiconductor wafers with an epitaxial layer are produced in a deposition chamber by placing a substrate wafer in the edge region of the rear side of the substrate wafer onto a placement area of a susceptor;

Method for producing a semiconductor wafer with epitaxial layer in a deposition chamber, apparatus for producing a semiconductor wafer with epitaxial layer, and semiconductor wafer with epitaxial layer

Epitaxially coated semiconductor wafers are prepared by a process in which a semiconductor wafer polished at least on its front side is placed on a susceptor in a single-wafer epitaxy reactor and epitaxially coated on its polished front side at temperatures of 1000-1200&#xb0; C., wherein, after coating, the semiconductor wafer is cooled in the temperature range from 1200&#xb0; C. to 900&#xb0; C. at a rate of less than 5&#xb0; C. per second. In a second method for producing an epitaxially coated wafer, the wafer is placed on a susceptor in the epitaxy reactor and epitaxially coated on its polished front side at a deposition temperature of 1000-1200&#xb0; C., and after coating, and while still at the deposition temperature, the wafer is raised for 1-60 seconds to break connections between susceptor and wafer produced by deposited semiconductor material before the wafer is cooled.

Method for producing an epitaxially coated semiconductor wafer

Epitaxially coated silicon wafers have a rounded and polished edge region and a region adjacent to the edge having a width of 3 mm on the front and rear sides, a surface roughness in edge region of 0.1-1.5 nm RMS relative to a spatial wavelength range of 10-80 &#x3bc;m, and a variation of surface roughness of 1-10%. The wafer edges, after polishing, are examined for defects and roughness at the edge and surrounding region. Silicon wafers having a surface roughness of less than 1 nm RMS are pretreated in single wafer epitaxy reactors, first in a hydrogen atmosphere at a flow rate of 1-100 slm and in a second step, an etching medium with a flow rate of 0.5-5 slm is conducted onto the edge region of the wafer by a gas distribution device. The wafer is then epitaxially coated.

Epitaxially coated silicon wafer and method for producing an epitaxially coated silicon wafer

A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate, and with addition of an etching medium to the hydrogen atmosphere at a reduced hydrogen flow rate in a second step, is subsequently coated epitaxially on its polished front side, and removed from the reactor. An etching treatment of the susceptor follows a specific number of epitaxial coatings. Silicon wafers produced thereby have a global flatness value GBIR of 0.07-0.3 &#x3bc;m relative to an edge exclusion of 2 mm.

Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers

Epitaxially coated silicon wafers, are produced by epitaxially coating a multiplicity of wafers polished at least on their front sides, successively and individually in an epitaxy reactor, by placing a silicon wafer on a susceptor, pretreating under a hydrogen atmosphere followed by addition of an etching medium to the hydrogen atmosphere, coating epitaxially on the polished front side and removing the water from the epitaxy reactor. The susceptor is then heated, in each case, to a temperature of at least 1000&#xb0; C. under a hydrogen atmosphere, and furthermore an etching treatment of the susceptor and a momentary coating of the susceptor with silicon are effected after a specific number of epitaxial coatings. Silicon wafers characterized by a parameter R30-1 mm of &#x2212;10 nm to +10 nm, determined at a distance of 1 mm from the edge of the silicon wafer are produced.

In a method for producing epitaxially coated semiconductor wafers, a multiplicity of prepared, front side-polished semiconductor wafers are successively coated individually with an epitaxial layer on their polished front sides at temperatures of 800-1200&#xb0; C. in a reactor, while supporting the prepared semiconductor wafer over a susceptor having a gas-permeable structure, on a ring placed on the susceptor which acts as a thermal buffer between the susceptor and the supported semiconductor wafer, the semiconductor wafer resting on the ring, and its backside facing but not contacting the susceptor, so that gaseous substances are delivered from a region over the backside of the semiconductor wafer by gas diffusion through the susceptor into a region over the backside of the susceptor, the semiconductor wafer contacting the ring only in an edge region of its backside, wherein no stresses measurable by means of photoelastic stress measurement ('SIRD') occur in the semiconductor wafer.

Epitaxially coated semiconductor wafer and device and method for producing an epitaxially coated semiconductor wafer

Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by placing a wafer on a susceptor, pretreating under a hydrogen atmosphere, in and then with addition of an etching medium, and coating epitaxially on a polished front side, wherein an etching treatment of the susceptor is effected after a specific number of epitaxial coatings, and the susceptor is then hydrophilized. Silicon wafer produced thereby have a maximum local flatness value SFQRof 0.01 &#x3bc;m to 0.035 &#x3bc;m relative to at least 99% of the partial regions of an area grid of measurement windows having a size of 26&#xd7;8 mmon the front side of the silicon wafer with an edge exclusion of 2 mm.

Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafer

A susceptor configured to receive a semiconductor wafer for deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD) has a gas-permeable structure with a porosity of at least 15%, a density of from 0.5 to 1.5 g/cm, a pore diameter of less than 0.1 mm and an internal surface area of the pores which is greater than 10,000 cm/cm. Semiconductor wafers having front surface coated by chemical vapor deposition (CVD) and a polished or etched back surface, prepared using the gas-permeable susceptor, have a nanotopography of the back surface, expressed as the PV (=peak to valley) height fluctuation, of less than 5 nm, and at the same time the halo of the back surface, expressed as haze, is less than 5 ppm.

Coated semiconductor wafer, and process and apparatus for producing the semiconductor wafer

A susceptor for a semiconductor wafer to be placed on during deposition of a layer on a front surface of the semiconductor wafer by chemical vapor deposition (CVD), has a gas-permeable structure with a porosity of at least 15% and a density of from 0.5 to 1.5 g/cm. There is also a semiconductor wafer having a back surface and a front surface which has been coated by chemical vapor deposition (CVD) and a polished or etched back surface. The nanotopography of the back surface, expressed as the height fluctuation PV (=peak to valley), is less than 5 nm. There is a process for producing the semiconductor wafer.

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Laufen, Germany

Reinhard Schauer