Infineon Technologies Ag

Infineon Technologies Austria Ag

Reinhard Mueller

Martin Feldtkeller

Jens Barrenscheen

Anthony Sanders

Torsten Hinz

Wolfgang Horchler

A power supply circuit is equipped with a converter circuit configured to convert an alternating current signal applied at an input of the power supply circuit into a direct current signal. A control circuit for the power supply circuit is configured to detect a phase of the alternating current signal and to control discharging of an internal capacitive element of the power supply circuit based on the detected phase of the alternating current signal.

Phase controlled discharging of internal capacitive element of power supply circuit

In some examples, a controller device is configured to control power electronics circuitry and includes a high-voltage (HV) pin, a power supply (VCC) pin, a startup device configured to conduct electricity from the HV pin to the VCC pin, and comparator circuitry configured to determine whether a voltage level of the VCC pin is greater than a turn-on voltage threshold. In some examples, the comparator circuitry is further configured to cause the controller device to enter a normal-operation mode in response to determining that the voltage level of the VCC pin is greater than the turn-on voltage threshold. In some examples, the controller device also includes level detection circuitry configured to determine the turn-on voltage threshold based on a level of the HV pin.

Controller device for power electronics circuit

A method for transmitting a digital data stream includes recovery of data clock information and data frame information from the digital data stream. The method includes providing a digital data stream having successive data stream units. Each data stream unit includes a data frame, a data block having data bits, and a frame synchronization word having frame synchronization bits. Successive frame synchronization words of the successive data stream units are then detected and data clock information is determined from a temporal spacing of the successive frame synchronization words. The data clock information is then output in a manner dependent on a temporal spacing of successive frame synchronization bits.

Recovering clock and frame information from data stream

An integrated full bridge circuit includes four transistors divided into two series-connected pairs of transistors each forming a half bridge circuit. Resistor elements each connect a respective one of the pairs of transistors to a reference potential. Other resistor elements are each connected to a respective one of two separate supply terminals inside a housing. Each of the other resistor elements is connected to one of the transistors of a respective one of the pairs of transistors at a junction. Driver transistors each have a load path with two connections and a type complementary to the transistors connected to the other resistor elements. One of the connections is connected upstream of the control terminal of a respective one of the transistors connected to the other resistor elements. The other of the connections in each of the half bridge circuits is connected to the junction in the other of the half bridge circuits. The advantage is power loss reduction.

Growing community of inventors

Unterhaching, Germany

Reinhard Mueller